LPC2106FHN48/01,55 NXP Semiconductors, LPC2106FHN48/01,55 Datasheet
LPC2106FHN48/01,55
Specifications of LPC2106FHN48/01,55
935286613551
LPC2106FHN48/01-S
Related parts for LPC2106FHN48/01,55
LPC2106FHN48/01,55 Summary of contents
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LPC2104/2105/2106 Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM Rev. 07 — 20 June 2008 1. General description The UART are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 128 ...
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... NXP Semiconductors I In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or full chip erase takes 400 ms. I Vectored Interrupt Controller with configurable priorities and vector addresses. I EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service routines can continue to execute whilst the foreground task is debugged with the on-chip RealMonitor software ...
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... NXP Semiconductors Table 1. Type number LPC2106FBD48/00 LPC2106FBD48/01 LPC2106FHN48 LPC2106FHN48/00 LPC2106FHN48/01 3.1 Ordering options Table 2. Type number LPC2104BBD48 LPC2104FBD48/00 LPC2104FBD48/01 LPC2105BBD48 LPC2105FBD48/00 LPC2105FBD48/01 LPC2106BBD48 LPC2106FBD48 LPC2106FBD48/00 LPC2106FBD48/01 LPC2106FHN48 LPC2106FHN48/00 LPC2106FHN48/01 LPC2104_2105_2106_7 Product data sheet Ordering information …continued Package Name Description LQFP48 plastic low profile quad flat package; 48 leads; ...
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... NXP Semiconductors 4. Block diagram LPC2104/2105/2106 HIGH-SPEED P0 (3) GPIO 32 PINS TOTAL ARM7 LOCAL BUS INTERNAL SRAM CONTROLLER 16/32/64 kB SRAM EXTERNAL (1) EINT[2:0] INTERRUPTS (1) CAP0[2:0] CAPTURE/ (1) CAP1[3:0] COMPARE (1) MAT0[2:0] TIMER 0/TIMER 1 (1) MAT1[3:0] GENERAL P0[31:0] PURPOSE I/O (1) PWM0 PWM[6:1] REAL-TIME CLOCK (1) Shared with GPIO. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning P0.19/MAT1.2/TCK P0.20/MAT1.3/TDI P0.21/PWM5/TDO V P0.27/TRACEPKT0/TRST P0.28/TRACEPKT1/TMS P0.29/TRACEPKT2/TCK Pin configuration is identical for all LQFP48 packages. Fig 2. Pin configuration (LQFP48) LPC2104_2105_2106_7 Product data sheet n. DD(1V8) RESET 6 LPC2104/2105/2106 XTAL1 11 12 XTAL2 Rev. 07 — 20 June 2008 LPC2104/2105/2106 Single-chip 32-bit microcontrollers 36 P0 ...
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... NXP Semiconductors terminal 1 index area P0.19/MAT1.2/TCK P0.20/MAT1.3/TDI P0.21/PWM5/TDO P0.27/TRACEPKT0/TRST P0.28/TRACEPKT1/TMS P0.29/TRACEPKT2/TCK Pin configuration is identical for LPC2106FHN48, LPC2106FHN48/00, and LPC2106FHN48/01. Fig 3. Pin configuration (HVQFN48) LPC2104_2105_2106_7 Product data sheet n. DD(1V8) RESET 6 LPC2104/2105/2106 XTAL1 11 12 XTAL2 Transparent top view Rev. 07 — 20 June 2008 ...
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... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin P0.0 to P0.31 [1] P0.0/TXD0/PWM1 13 [1] P0.1/RXD0/PWM3 14 [2] P0.2/SCL/CAP0.0 18 [2] P0.3/SDA/MAT0.0 21 [1] P0.4/SCK/CAP0.1 22 [1] P0.5/MISO/MAT0.1 23 [1] P0.6/MOSI/CAP0.2 24 [1] P0.7/SSEL/PWM2 28 [1] P0.8/TXD1/PWM4 29 [1] P0.9/RXD1/PWM6 30 [1] P0.10/RTS1/CAP1.0 35 LPC2104_2105_2106_7 Product data sheet Type Description I/O Port 0: Port 32-bit bidirectional I/O port with individual direction controls for each bit ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [1] P0.11/CTS1/CAP1.1 36 [1] P0.12/DSR1/MAT1.0 37 [1] P0.13/DTR1/MAT1.1 41 [1] P0.14/DCD1/EINT1 44 [1] P0.15/RI1/EINT2 45 [1] P0.16/EINT0/MAT0.2 46 [1] P0.17/CAP1.2/TRST 47 [1] P0.18/CAP1.3/TMS 48 [1] P0.19/MAT1.2/TCK 1 [1] P0.20/MAT1.3/TDI 2 [1] P0.21/PWM5/TDO 3 [4] P0.22/TRACECLK 32 [4] P0.23/PIPESTAT0 33 [4] P0.24/PIPESTAT1 34 [4] P0.25/PIPESTAT2 38 LPC2104_2105_2106_7 Product data sheet ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [4] P0.26/TRACESYNC 39 [4] P0.27/TRACEPKT0/ 8 TRST [4] P0.28/TRACEPKT1/ 9 TMS [4] P0.29/TRACEPKT2/ 10 TCK [4] P0.30/TRACEPKT3/ 15 TDI [4] P0.31/EXTIN0/TDO 16 [4] RTCK 26 DBGSEL 27 [5] RESET 6 XTAL1 11 XTAL2 19 DD(1V8) V 17, 40 DD(3V3) n.c. 4, 20, 25 tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. ...
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... NXP Semiconductors 6. Functional description 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers ...
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... NXP Semiconductors 6.4 Memory map The LPC2104/2105/2106 memory maps incorporate several distinct regions, as shown in the following figures. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip static RAM. This is described in “System (1) LPC2104/2105/2106/01 only. Fig 4. ...
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... NXP Semiconductors 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the Interrupt Request (IRQ) inputs and categorizes, them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. ...
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... NXP Semiconductors Table 4. Block UART 1 PWM0 2 I C-bus SPI and SSP - PLL RTC System Control System Control System Control [1] Available on LPC2104/2105/2106/01 only. 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals ...
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... NXP Semiconductors Table 6. PINSEL0 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 LPC2104_2105_2106_7 Product data sheet Pin function select register 0 (PINSEL0 - 0xE002 C000) Pin name Value P0. P0. P0. Rev. 07 — 20 June 2008 ...
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... NXP Semiconductors Table 6. PINSEL0 27:26 29:28 31:30 6.8 Pin function select register 1 (PINSEL1 - 0xE002 C004) The PINSEL1 register controls the functions of the pins as per the settings listed in Table 7. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. ...
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... NXP Semiconductors Table 7. PINSEL1 25:24 27:26 29:28 31:30 6.9 General purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins ...
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... NXP Semiconductors • Standard modem interface signals included on UART 1. 6.10.2 UART features available in LPC2104/2105/2106/01 only Compared to previous LPC2000 microcontrollers, UARTs in LPC2104/2105/2106/01 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS fl ...
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... NXP Semiconductors 6.12 SPI serial I/O controller The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master ...
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... NXP Semiconductors 6.14.1 Features • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. • four (Timer 1) and three (Timer 0) 32-bit capture channels, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. • Four 32-bit match registers that allow: – ...
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... NXP Semiconductors • Programmable 32-bit timer with internal pre-scaler. • Selectable time period from (T T cy(PCLK) 6.16 Real time clock The Real Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode) ...
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... NXP Semiconductors With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge) ...
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... NXP Semiconductors produce the output clock. Since the minimum output divider value insured that the PLL output has duty cycle.The PLL is turned off and bypassed following a chip Reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100 s ...
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... NXP Semiconductors 3. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too the user’s application to provide (if needed) a flash update mechanism using IAP calls or a call to reinvoke ISP command to enable flash update via UART 0 ...
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... NXP Semiconductors processor clock rate. The second purpose of the APB divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode ...
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... NXP Semiconductors 6.19.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real time debug lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC (Debug Communications Channel), which is present in the EmbeddedICE logic. The LPC2104/2105/2106 contain a specifi ...
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... NXP Semiconductors 7. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V input voltage I I supply current DD I ground current SS T storage temperature stg P total power dissipation (per ...
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... NXP Semiconductors 8. Static characteristics Table 9. Static characteristics +70 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) Standard port pins, RESET, RTCK, and DBGSEL I LOW-state input current IL I HIGH-state input current IH I OFF-state output current ...
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... NXP Semiconductors Table 9. Static characteristics +70 C for commercial applications, unless otherwise specified. amb Symbol Parameter LPC2104/2105/2106 and LPC2104/2105/2106/00 power consumption I active mode supply current V DD(act) I Power-down mode supply DD(pd) current LPC2104/2105/2106/01 power consumption I active mode supply current V DD(act) I Idle mode supply current ...
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... NXP Semiconductors Table 9. Static characteristics +70 C for commercial applications, unless otherwise specified. amb Symbol Parameter Oscillator pins V input voltage on pin XTAL1 i(XTAL1) V output voltage on pin o(XTAL2) XTAL2 [1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), nominal supply voltages. ...
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... NXP Semiconductors I DD(act) (mA) Fig 6. I DD(idle) (mA) Fig 7. LPC2104_2105_2106_7 Product data sheet 1.65 1.70 1.75 Test conditions: Active mode entered executing code from on-chip flash; PCLK = all peripherals enabled. amb Typical LPC2104/2105/2106/01 I 15.0 10.0 all peripherals enabled all peripherals disabled 5.0 0.0 ...
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... NXP Semiconductors I DD(idle) (mA) Fig 8. I DD(act) (mA) Fig 9. LPC2104_2105_2106_7 Product data sheet 15.0 10.0 5.0 0.0 1.65 1.70 1.75 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = all peripherals enabled. amb Typical LPC2104/2105/2106/ MHz 48 MHz MHz Test conditions: Active mode entered executing code from on-chip flash; PCLK = voltage 1.8 V ...
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... NXP Semiconductors I DD(Idle) (mA) Fig 10. Typical LPC2104/2105/2106/ DD(pd Fig 11. Typical LPC2104/2105/2106/01 core power-down current I Table 10. Core voltage 1 Peripheral Timer 0 Timer 1 UART 0 UART 1 LPC2104_2105_2106_7 Product data sheet 6.0 60 MHz 48 MHz 4.0 2.0 12 MHz 0 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = 1.8 V ...
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... NXP Semiconductors Table 10. Peripheral PWM0 2 I C-bus SPI RTC SSP LPC2104_2105_2106_7 Product data sheet Typical LPC2104/2105/2106/01 peripheral power consumption in Idle mode …continued Rev. 07 — 20 June 2008 LPC2104/2105/2106 Single-chip 32-bit microcontrollers CCLK = 60 MHz 0.511 0.078 0.060 0.109 0.377 © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors 9. Dynamic characteristics Table 11. Dynamic characteristics +70 C for commercial applications +85 C for industrial applications; V amb [1] specified ranges. Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time ...
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... NXP Semiconductors 9.1 Timing Fig 12. External clock timing (with an amplitude of at least V LPC2104_2105_2106_7 Product data sheet LPC2104/2105/2106 t CHCX CHCL CLCX CLCH T cy(clk) = 200 mV) i(RMS) Rev. 07 — 20 June 2008 Single-chip 32-bit microcontrollers 002aaa907 © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 10. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 11. Abbreviations Table 12. Acronym AMBA APB CPU DCC FIFO GPIO PLL PWM RAM SPI SSI SSP SRAM TTL UART LPC2104_2105_2106_7 Product data sheet Abbreviations Description Advanced Microcontroller Bus Architecture ARM Peripheral Bus Central Processing Unit Debug Communications Channel First In, First Out ...
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... Data sheet status Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3 “Ordering information”; corrected temperature range for LPC2104FBD48/00, LPC2105FBD48/00 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 New features implemented in LPC2104/2105/2106/01 devices 2.2 Key common features . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Functional description . . . . . . . . . . . . . . . . . . 10 6.1 Architectural overview 6.2 On-chip fl ...