EP9315-CB Cirrus Logic Inc, EP9315-CB Datasheet - Page 193

• Manufacturer Part Number: EP9315-CB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1261

DS785UM1
7.4.5 Color Look-Up-Tables
7.4.6 Color RGB Mux
this mode will cause an object to appear and disappear. A drawback to this mode is that it
may cause problems with correctly viewing overlapping objects. Blink Brighter and Blink
Dimmer modes shift the pixel data values by one bit position. For Blink Brighter, the LSB is
dropped, the MSBs are all shifted one bit lower, and the MSB is set to a “1”. For Blink
Dimmer, the LSB is dropped, the MSBs are all shifted one bit lower, and the MSB is set to a
“0“. Blink to Offset is simply adding the value in the BkgrndOffset register to blinking pixels.
The shifting and offsetting can be programmed to be compatible with the selected pixel
organization mode.
Defining blink pixels in 16 bpp and
colors available. A blinking pixel is defined by the
By using the PattrnMask register, either multiple or single bit planes may be used to specify
blinking pixels. This will allow the number of definable blinking pixels to range from all pixel
combinations blinking to only one pixel that blinks. This approach allows the option of
minimizing the number of lost colors by reducing the number of blinking colors. BlinkPattrn is
then used to define the value of the PATTRNMASK bits in the
should blink.
The Raster Engine contains two 256 x 24-bit RAMs that are used as color pixel LUTs to
provide a selection of 256 colors from a palette of 16 million colors. One LUT is inserted in the
video pipeline, while the other is accessible via the AHB. Changing the SWITCH bit in the
“LUTSwCtrl”
The LUTs are mapped to memory addresses and are accessible from the AHB one at a time.
During active video display, the LUT switch command is synchronized to the beginning of the
next vertical frame. When the video state machine is disabled the LUT switch occurs almost
immediately. The status of actual switch occurrence can be monitored by reading the SSTAT
bit in the
and used to time the switching. Each LUT can be used for 4 bpp and 8 bpp modes and is
usually bypassed for 16 bpp and 24 bpp modes. Control for whether or not the LUTs are used
or bypassed altogether in the video pipeline is performed by writing to the appropriate value
to C field (Color field) in the
The color RGB mux is necessary for selecting the appropriate pixel format and routing it to
the appropriate video output stream. The Color RGB mux formats data for the pixel shift logic,
a color DAC interface, or the YCrCb interface. The color RGB mux primary mode of operation
is controlled by the “C” value (color value) in the
operation selects data from the grayscale generator, from the LUT, or from the video pipeline
after the blink logic. When the hardware cursor is enabled by writing CLHEN = ‘1’ in the
“CursorDScanLHYLoc”
CursorColor1/2
may be inverted. The data formatting performed by the color RGB mux also depends on the
“C” value (color value) in the
the pixel data is reformatted to fit into a 24-bit bus. This includes copying the MSBs for the
“LUTSwCtrl”
register toggles which LUT is in the pipe and which is accessible by the AHB.
data values may be injected into the pipeline, or the primary incoming data
register. This bit can be polled, or the frame interrupt can be enabled
register or CursorXYLoc.CEN = ‘1’ in the
“PixelMode”
“PixelMode”
Copyright 2007 Cirrus Logic
24 bpp
Raster Engine With Analog/LCD Integrated Timing and Interface
register.
register. When in 16-bit 555 or 565 data modes,
modes also may sacrifice the total number of
“PixelMode”
“PattrnMask”
register. The primary mode of
“BlinkPattrn”
and
“CursorXYLoc”
“PattrnMask”
EP93xx User’s Guide
register that
register,
registers.
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