C8051F369-GM Silicon Laboratories Inc, C8051F369-GM Datasheet - Page 181

• Manufacturer Part Number: C8051F369-GM
• Description: IC 8051 MCU 16K FLASH 28-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F369-GM

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 21
• Height: 0.83 mm
• Length: 5 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1651

Bits 7–0: PLLN7–0: PLL Multiplier.
SFR Page:
SFR Address:
Bits 7–6: UNUSED. Read = 00b. Write = don’t care.
Bits 5–4: PLLICO1-0: PLL Current-Controlled Oscillator Control Bits.
Bits 3–0: PLLLP3-0: PLL Loop Filter Control Bits.
SFR Page:
SFR Address:
PLLN7
R/W
Bit7
R/W
Bit7
–
These bits select the multiplication factor of the divided PLL reference clock. When set to
any non-zero value, the multiplication factor will be equal to the value in PLLN7-0. When set
to ‘00000000b’, the multiplication factor will be equal to 256.
Selection is based on the desired output frequency, according to the following table:
Selection is based on the divided PLL reference clock, according to the following table:
All other states of PLLLP3–0 are RESERVED.
F
0xB1
F
0xB2
PLLN6
Divided PLL Reference Clock
R/W
Bit6
R/W
Bit6
–
SFR Definition 16.8. PLL0MUL: PLL Clock Scaler
PLL Output Clock
12.2–19.5 MHz
7.8–12.5 MHz
65–100 MHz
PLLICO1 PLLICO0
45–80 MHz
30–60 MHz
25–50 MHz
19–30 MHz
PLLN5
SFR Definition 16.9. PLL0FLT: PLL Filter
5–8 MHz
R/W
Bit5
R/W
Bit5
PLLN4
R/W
Bit4
R/W
Bit4
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
PLLLP3
PLLN3
R/W
Bit3
R/W
Bit3
PLLLP2
PLLN2
R/W
Bit2
R/W
Bit2
PLLICO1-0
PLLLP3-0
0001
0011
0111
1111
00
01
10
11
PLLLP1
PLLN1
R/W
Bit1
R/W
Bit1
PLLLP0 00110001
PLLN0
R/W
Bit0
R/W
Bit0
00000001
Reset Value
Reset Value
181