C8051F369-GM Silicon Laboratories Inc, C8051F369-GM Datasheet - Page 91

• Manufacturer Part Number: C8051F369-GM
• Description: IC 8051 MCU 16K FLASH 28-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F369-GM

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 21
• Height: 0.83 mm
• Length: 5 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1651

While in the ADC0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority
interrupt, while the ADC0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector
to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place SFR page 0x00 into the
SFRPAGE register. The value that was in the SFRPAGE register before the PCA interrupt (SFR Page 0x00
for ADC0) is pushed down the stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register
before the PCA interrupt (in this case SFR Page 0x0F for OSCICN) is pushed down to the SFRLAST reg-
ister, the “bottom” of the stack. Note that a value stored in SFRLAST (via a previous software write to the
SFRLAST register) will be overwritten. See Figure 9.6 below.
Figure 9.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC0 ISR
Figure 9.5. SFR Page Stack After ADC0 Window Comparator Interrupt Occurs
SFRPAGE
SFRNEXT
pushed to
SFRPAGE
SFRNEXT
pushed to
SFRNEXT
SFRLAST
pushed to
SFRPAGE on ADC0
(OSCICN)
pushed on stack in
(OSCICN)
SFR Page 0x00
SFRPAGE on PCA
(ADC0)
pushed on stack in
Automatically
SFR Page 0x00
(ADC0)
0x00
0x0F
Automatically
(PCA)
interrupt
0x00
0x00
0x0F
interrupt
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
SFRPAGE
SFRNEXT
SFRLAST
SFRPAGE
SFRNEXT
SFRLAST
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