M30622F8PFP#U3C Renesas Electronics America, M30622F8PFP#U3C Datasheet - Page 32

IC M16C MCU FLASH 64K 100QFP

M30622F8PFP#U3C

Manufacturer Part Number
M30622F8PFP#U3C
Description
IC M16C MCU FLASH 64K 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30622F8PFP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M16C/62P Group (M16C/62P, M16C/62PT)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
b31
R2
R3
b15
NOTES:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
Central Processing Unit Register
2.1
Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data
register (R2R0). R3R1 is the same as R2R0.
Rev.2.41
Jan 10, 2006
Page 30 of 96
REJ03B0001-0241
b15
b8 b7
R0H
R0L
R1H
R1L
R2
R3
A0
A1
FB
b19
b15
INTBH
INTBL
b19
PC
b15
USP
ISP
SB
b15
FLG
b8
b7
IPL
U
I
O
B
S
2. Central Processing Unit (CPU)
b0
(1)
Data Registers
(1)
Address Registers
(1)
Frame Base Registers
b0
Interrupt Table Register
b0
Program Counter
b0
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
b0
Flag Register
b0
Z
D
C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area

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