M30622F8PFP#U3C Renesas Electronics America, M30622F8PFP#U3C Datasheet - Page 83

IC M16C MCU FLASH 64K 100QFP

M30622F8PFP#U3C

Manufacturer Part Number
M30622F8PFP#U3C
Description
IC M16C MCU FLASH 64K 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30622F8PFP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M16C/62P Group (M16C/62P, M16C/62PT)
Memory Expansion Mode, Microprocessor Mode
(
For 3-wait setting, external area access and multiplex bus selection
Read timing
t
cyc
BCLK
t
d(BCLK-CS)
40ns.max
CSi
t
d(AD-ALE)
(0.5×t
-40)ns.min
cyc
ADi
Address
/DBi
t
d(BCLK-AD)
t
d(AD-RD)
40ns.max
0ns.min
ADi
BHE
(No multiplex)
t
d(BCLK-ALE)
40ns.max
t
h(BCLK-ALE)
-4ns.min
ALE
RD
Write timing
t
cyc
BCLK
t
d(BCLK-CS)
40ns.max
CSi
ADi
Address
/DBi
t
d(AD-ALE)
(0.5×t
-40)ns.min
cyc
t
d(BCLK-AD)
40ns.max
ADi
BHE
(No multiplex)
t
t
d(BCLK-ALE)
h(BCLK-ALE)
40ns.max
-4ns.min
ALE
WR, WRL
WRH
1
t
=
cyc
f(BCLK)
Measuring conditions
· V
=V
=3V
CC1
CC2
· Input timing voltage : V
IL
· Output timing voltage : V
Figure 5.21
Timing Diagram (9)
Rev.2.41
Jan 10, 2006
Page 81 of 96
REJ03B0001-0241
)
t
h(ALE-AD)
(0.5×t
-15)ns.min
cyc
t
dZ(RD-AD)
t
8ns.max
ac3(RD-DB)
(2.5×t
-60)ns.max
cyc
t
d(BCLK-RD)
40ns.max
t
d(BCLK-DB)
50ns.max
Data output
t
d(DB-WR)
(2.5×t
-50)ns.min
cyc
t
d(AD-WR)
0ns.min
t
d(BCLK-WR)
40ns.max
=0.6V, V
=2.4V
IH
=1.5V, V
=1.5V
OL
OH
5. Electrical Characteristics
V
=V
=3V
CC1
CC2
t
h(RD-CS)
t
h(BCLK-CS)
(0.5×t
-10)ns.min
cyc
6ns.min
Data input
t
h(RD-DB)
0ns.min
t
t
su(DB-RD)
h(BCLK-AD)
50ns.min
4ns.min
t
h(RD-AD)
(0.5×t
-10)ns.min
cyc
t
h(BCLK-RD)
0ns.min
t
h(WR-CS)
t
h(BCLK-CS)
(0.5×t
-10)ns.min
cyc
4ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5×t
-10)ns.min
cyc
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5×t
-10)ns.min
cyc
t
h(BCLK-WR)
0ns.min

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