IC M16C MCU FLASH 64K 100QFP

M30622F8PFP#U3C

Manufacturer Part NumberM30622F8PFP#U3C
DescriptionIC M16C MCU FLASH 64K 100QFP
ManufacturerRenesas Electronics America
SeriesM16C™ M16C/60
M30622F8PFP#U3C datasheets
 


Specifications of M30622F8PFP#U3C

Core ProcessorM16C/60Core Size16-Bit
Speed24MHzConnectivityI²C, IEBus, UART/USART
PeripheralsDMA, WDTNumber Of I /o85
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Ram Size4K x 8Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 V
Data ConvertersA/D 26x10b; D/A 2x8bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case100-QFP
For Use With867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30PLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-  
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M16C/62P Group (M16C/62P, M16C/62PT)
Memory Expansion Mode, Microprocessor Mode
(For 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
t
d(BCLK-CS)
40ns.max
CSi
t
d(AD-ALE)
(0.5×t
-40)ns.min
cyc
ADi
/DBi
t
d(BCLK-AD)
40ns.max
ADi
BHE
t
d(BCLK-ALE)
40ns.max
ALE
RD
Write timing
BCLK
t
d(BCLK-CS)
40ns.max
CSi
ADi
/DBi
t
d(AD-ALE)
(0.5×t
-40)ns.min
cyc
t
d(BCLK-AD)
40ns.max
ADi
BHE
t
d(BCLK-ALE)
40ns.max
ALE
WR,WRL,
WRH
1
t
=
cyc
f(BCLK)
Measuring conditions
· V
=V
=3V
CC1
CC2
· Input timing voltage : V
· Output timing voltage : V
Figure 5.20
Timing Diagram (8)
Rev.2.41
Jan 10, 2006
Page 80 of 96
REJ03B0001-0241
t
cyc
t
h(ALE-AD)
(0.5×t
-15)ns.min
cyc
Address
t
dZ(RD-AD)
8ns.max
t
ac3(RD-DB)
(1.5×t
-60)ns.max
cyc
t
d(AD-RD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
40ns.max
t
cyc
t
d(BCLK-DB)
50ns.max
Address
Data output
t
d(DB-WR)
(1.5×t
-50)ns.min
cyc
t
t
d(AD-WR)
h(BCLK-ALE)
-4ns.min
0ns.min
t
d(BCLK-WR)
40ns.max
=0.6V, V
=2.4V
IL
IH
=1.5V, V
=1.5V
OL
OH
5. Electrical Characteristics
V
=V
=3V
CC1
CC2
t
h(BCLK-CS)
t
h(RD-CS)
4ns.min
(0.5×t
-10)ns.min
cyc
Address
Data input
t
h(RD-DB)
t
su(DB-RD)
0ns.min
50ns.min
t
h(BCLK-AD)
4ns.min
t
h(RD-AD)
(0.5×t
-10)ns.min
cyc
t
h(BCLK-RD)
0ns.min
t
t
h(BCLK-CS)
h(WR-CS)
4ns.min
(0.5×t
-10)ns.min
cyc
t
h(BCLK-DB)
4ns.min
Address
t
h(WR-DB)
(0.5×t
-10)ns.min
cyc
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5×t
-10)ns.min
cyc
t
h(BCLK-WR)
0ns.min