MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 17

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.4.4.1
The MCF5407 processor supports seven addressing modes (refer to Table 5). Register indirect addressing
modes support postincrement, predecrement, offset, and indexing, which are particularly useful for handling
data structures common to sophisticated embedded applications and high-level languages. The program
counter indirect mode also has indexing and offset capabilities. This addressing mode is typically required
to support position-independent code. As part of the indexed addressing mode, ColdFire architecture
supports an optional scale factor that can be applied to the index register to easily access byte, word, or
longword entries within an array (x1, x2, x4).
An instruction’s effective addressing mode can specify the operand in one of three ways:
Each addressing mode has a unique assembler syntax. In addition to the generalized format where the
addressing mode is specified directly in the instruction, some opcodes implicitly define the effective
address. Table 5 summarizes supported effective addressing modes.
MOTOROLA
Instruction
•
•
•
Address
MSW
LSW
MSB
LSB
msb
Bit
lsb
d
{}
()
C
N
V
X
Z
It can specify the data value directly as an immediate operand
It can specify the register containing the operand
It can specify the addressing calculation needed to reference the memory location containing the
operand
n
Addressing Capability Summary
Optional operation
Identifies an indirect address
Displacement value, n-bits wide (example: d
Calculated effective address (pointer)
Bit selection (example: Bit 3 of D0)
Least significant bit (example: lsb of D0)
Least significant byte
Least significant word
Most significant bit
Most significant byte
Most significant word
Carry
Negative
Overflow
Extend
Zero
MCF5407 Integrated ColdFire® Microprocessor Product Brief
Freescale Semiconductor, Inc.
Table 4. Notational Conventions (continued)
For More Information On This Product,
Condition Code Register Bit Names
Go to: www.freescale.com
Programming Model, Addressing Modes, and Instruction Set
Subfields and Qualifiers
Operand Syntax
16
is a 16-bit displacement)
17