ATTINY25-20SH Atmel, ATTINY25-20SH Datasheet - Page 65

• Manufacturer Part Number: ATTINY25-20SH
• Description: IC MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SH

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Processor Series: ATtiny
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2586M–AVR–07/10
Table 10-4
shown in
Table 10-4.
Note:
Table 10-5.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
1. 1 when the Fuse is “0” (Programmed).
Figure 10-5 on page
PB5/RESET/
ADC0/PCINT5
RSTDISBL
1
RSTDISBL
debugWire Transmit
0
0
0
RSTDISBL
PCIE + ADC0D)
ADC0D
PCINT5 Input
RESET Input, ADC0 Input
PB2/SCK/ADC1/T0/
USCK/SCL/INT0/PCINT2
USI_TWO_WIRE
0
USI_TWO_WIRE
(USI_SCL_HOLD +
PORTB2) • DDB2
USI_TWO_WIRE • DDB2
0
USITC
PCINT2 • PCIE + ADC1D +
USISIE
ADC1D
T0/USCK/SCL/INT0/
PCINT2 Input
ADC1 Input
and
Overriding Signals for Alternate Functions in PB[5:3]
Overriding Signals for Alternate Functions in PB[2:0]
Table 10-5
(1)
(1)
(1)
• DWEN
• DWEN
+ (PCINT5 •
relate the alternate functions of Port B to the overriding signals
60.
(1)
(1)
PB4/ADC2/XTAL2/
OC1B/PCINT4
0
0
0
0
OC1B Enable
OC1B
0
PCINT4 • PCIE + ADC2D
ADC2D
PCINT4 Input
ADC2 Input
PB1/MISO/DO/AIN1/
OC1A/OC0B/PCINT1
0
0
0
0
OC0B Enable + OC1A
Enable +
USI_THREE_WIRE
OC0B + OC1A + DO
0
PCINT1 • PCIE + AIN1D
AIN1D
PCINT1 Input
Analog Comparator
Negative Input
PB3/ADC3/XTAL1/
OC1B/PCINT3
0
0
0
0
OC1B Enable
OC1B
0
PCINT3 • PCIE + ADC3D
ADC3D
PCINT3 Input
ADC3 Input
PB0/MOSI/DI/SDA/AIN0/AR
EF/OC1A/OC0A/
PCINT0
USI_TWO_WIRE
0
USI_TWO_WIRE
(SDA + PORTB0) • DDB0
OC0A Enable + OC1A
Enable + (USI_TWO_WIRE
• DDB0)
OC0A + OC1A
0
PCINT0 • PCIE + AIN0D +
USISIE
AIN0D
DI/SDA/PCINT0 Input
Analog Comparator Positive
Input
65