PIC12C671T-04E/SM Microchip Technology, PIC12C671T-04E/SM Datasheet - Page 164

• Manufacturer Part Number: PIC12C671T-04E/SM
• Description: IC MCU OTP 1KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C671T-04E/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PICmicro MID-RANGE MCU FAMILY
10.3
DS31010A-page 10-4
Operation
A write to the PSP from the external system, occurs when both the CS and WR lines are first
detected low. When either the CS or WR lines become high (edge triggered), the Input Buffer Full
status flag bit IBF (TRISE<7>) is set on the Q4 clock cycle, following the next Q2 cycle, to signal
the write is complete. The interrupt flag bit, PSPIF, is also set on the same Q4 clock cycle. The
IBF flag bit is inhibited from being cleared for additional T
flag bit is cleared by reading the PORTD input latch, and this has to be a read-only instruction
(i.e., MOVF) and not a read-modify-write instruction. The input Buffer Overflow status flag bit IBOV
(TRISE<5>) is set if a second write to the Parallel Slave Port is attempted when the previous byte
has not been read out of the buffer.
A read from the PSP from the external system, occurs when both the CS and RD lines are first
detected low. The Output Buffer Full status flag bit OBF (TRISE<6>) is cleared immediately indi-
cating that the PORTD latch was read by the external bus. When either the CS or RD pin
becomes high (edge triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following
the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to
PORTD by the user firmware.
Input Buffer Full Status Flag bit IBF, is set if a received word is waiting to be read by the CPU.
Once the PORT input latch is read, the IBF bit is cleared. The IBF bit is a read only status bit.
Output Buffer Full Status Flag bit OBF, is set if a word written to PORT latch is waiting to be read
by the external bus. Once the PORTD output latch is read by the microprocessor, OBF is cleared.
Input Buffer Overflow Status Flag bit IBOV is set if a second write to the microprocessor port is
attempted when the previous word has not been read by the CPU (the first word is retained in
the buffer).
When not in Parallel Slave Port mode, the IBF and OBF bits are held clear. However, if flag bit
IBOV was previously set, it must be cleared in the software.
An interrupt is generated and latched into flag bit PSPIF when a read or a write operation is com-
pleted. Interrupt flag bit PSPIF must be cleared by user software and the interrupt can be dis-
abled by clearing interrupt enable bit PSPIE.
Table 10-1: PORTE Functions
RD
WR
CS
Note:
Name
The PSP may have other functions multiplexed onto the same pins. For the PSP to
operate, the pins must be configured as digital I/O.
Read Control Input in parallel slave port mode:
Write Control Input in parallel slave port mode:
Chip Select Control Input in parallel slave port mode:
WR
RD
CS
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
1 = Device is not selected
0 = Device is selected
Function
CY
cycles (see
1997 Microchip Technology Inc.
parameter
66). If the IBF