PIC12C671T-04E/SM Microchip Technology, PIC12C671T-04E/SM Datasheet - Page 273

• Manufacturer Part Number: PIC12C671T-04E/SM
• Description: IC MCU OTP 1KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C671T-04E/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

16.5
16.5.1
1997 Microchip Technology Inc.
SSP Module / Basic SSP Module Compatibility
Initialization
Example 16-2: SPI Master Mode Initialization
When changing from the SSP Module to the Basic SSP module, the SSPSTAT register contains
two additional control bits. These bits are:
• SMP, SPI data input sample phase
• CKE, SPI Clock Edge Select
To be compatible with the SPI of the Basic SSP module, these bits must be appropriately config-
ured. If these bits are not at the states shown in
be expected. If the SSP module uses a different configuration then shown in
Basic SSP module can not be used to implement that mode. That mode may be implemented in
software.
Table 16-4: New Bit States for Compatibility
Basic SSP Module
CLRF
CLRF
MOVLW
MOVWF
BSF
BSF
BCF
BSF
MOVLW
MOVWF
CKP
1
0
STATUS
SSPSTAT
0x31
SSPCON
STATUS, RP0
PIE1, SSPIE
STATUS, RP0
INTCON, GIE
DataByte
SSPBUF
CKP
; Bank 0
; Clear status bits
; Set up SPI port, Master mode, CLK/16,
;
;
; Bank 1
; Bank 0
; Enable, enabled interrupts
; Data to be Transmitted
;
; Start Transmission
; Enable SSP interrupt
1
0
Data xmit on rising edge
Data sampled in middle
Could move data from RAM location
SSP Module
CKE
0
0
Table
Section 16. BSSP
16-4, improper SPI communication should
SMP
0
0
DS31016A-page 16-23
Table
16-4, the
16