ATTINY24-15MZ Atmel, ATTINY24-15MZ Datasheet - Page 118

• Manufacturer Part Number: ATTINY24-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.11.9
118
Atmel ATtiny24/44/84 [Preliminary]
TIFR1 – Timer/Counter Interrupt Flag Register 1
• Bit 7,6,4,3 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must
be written to logical zero when the register is written.
• Bit 5– ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the input capture register
(ICR1) is set by the WGM13:0 to be used as the top value, the ICF1 flag is set when the coun-
ter reaches the top value.
ICF1 is automatically cleared when the input capture interrupt vector is executed. Alterna-
tively, ICF1 can be cleared by writing a logical one to its bit location.
• Bit 2– OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the output
compare register B (OCR1B).
Note that a forced output compare (1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the output compare match B interrupt vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logical one to its bit location.
• Bit 1– OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the output
compare register A (OCR1A).
Note that a forced output compare (1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the output compare match A interrupt vector is exe-
cuted. Alternatively, OCF1A can be cleared by writing a logical one to its bit location.
• Bit 0– TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bit settings. In normal and CTC modes,
the TOV1 flag is set when the timer overflows. See
behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the timer/counter 1 overflow interrupt vector is executed.
Alternatively, TOV1 can be cleared by writing a logical one to its bit location.
Bit
0x0B (0x2B)
Read/Write
Initial Value
–
R
7
0
–
R
6
0
ICIF1
R/W
5
0
–
R
4
0
–
Table 14-4 on page 114
R
3
0
OCF1B
R/W
2
0
OCF1A
R/W
1
0
TOV1
for the TOV1 flag
R/W
0
0
7701D–AVR–09/10
TIFR1