ATTINY24-15MZ Atmel, ATTINY24-15MZ Datasheet - Page 71

• Manufacturer Part Number: ATTINY24-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. 8-bit Timer/Counter0 with PWM
13.1
13.2
13.2.1
7701D–AVR–09/10
Features
Overview
Registers
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Timer/counter 0 is a general purpose 8-bit timer/counter module, with two independent out-
put compare units, and with PWM support. It allows accurate program execution timing (event
management) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in
the actual placement of I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit
locations are listed in the
Figure 13-1. 8-bit Timer/Counter Block Diagram
The timer/counter (TCNT0) and output compare registers (OCR0A and OCR0B) are 8-bit reg-
isters. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
timer/counter 0 interrupt flag register (TIFR0). All interrupts are individually masked with the
timer interrupt mask register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source
on the T0 pin. The Clock Select logic block controls which clock source and edge the
Two Independent Output Compare Units
Double Buffered Output Compare Registers
Clear Timer on Compare Match (Auto Reload)
Glitch Free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
Timer/Counter
“Register Description” on page
TCCRnA
OCRnA
TCNTn
OCRnB
Atmel ATtiny24/44/84 [Preliminary]
=
=
Direction
Count
Clear
Control Logic
Figure 1-1 on page
TOP
=
TCCRnB
Value
BOTTOM
Fixed
TOP
clk
=
Tn
0
83.
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TOVn
(Int.Req.)
Clock Select
Generation
Generation
2. CPU accessible I/O Registers,
( From Prescaler )
Waveform
Waveform
Detector
Edge
Figure 13-1 on page
OCnA
OCnB
Tn
71. For
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