ATMEGA164P-20AQ Atmel, ATMEGA164P-20AQ Datasheet - Page 30

• Manufacturer Part Number: ATMEGA164P-20AQ
• Description: MCU AVR 16K FLASH 20MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA164P-20AQ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1.3
6.1.4
6.1.5
6.2
6.2.1
6.2.2
8011O–AVR–07/10
Clock Sources
Flash Clock – clk
Asynchronous Timer Clock – clk
ADC Clock – clk
Default Clock Source
Clock Startup Sequence
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows
using this Timer/Counter as a real-time counter even when the device is in sleep mode.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-1.
Note:
The device is shipped with internal RC oscillator at 8.0 MHz and with the fuse CKDIV8 pro-
grammed, resulting in 1.0 MHz system clock. The startup time is set to maximum and time-out
period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that
all users can make their desired clock source setting using any available programming interface.
Any clock source needs a sufficient V
cycles before it can be considered stable.
To ensure sufficient V
the device reset is released by all other reset sources.
describes the start conditions for the internal reset. The delay (t
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
ADC
Device Clocking Option
Low Power Crystal Oscillator
Full Swing Crystal Oscillator
Low Frequency Crystal Oscillator
Internal 128 kHz RC Oscillator
Calibrated Internal RC Oscillator
External Clock
Reserved
FLASH
1. For all fuses “1” means unprogrammed while “0” means programmed.
Device Clocking Options Select
ASY
CC
, the device issues an internal reset with a time-out delay (t
CC
to start oscillating and a minimum number of oscillating
(1)
ATmega164P/324P/644P
”On-chip Debug System” on page 46
TOUT
) is timed from the Watchdog
1111 - 1000
0111 - 0110
0101 - 0100
CKSEL3..0
0011
0010
0000
0001
TOUT
) after
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