ATMEGA164P-20AQ Atmel, ATMEGA164P-20AQ Datasheet - Page 334

• Manufacturer Part Number: ATMEGA164P-20AQ
• Description: MCU AVR 16K FLASH 20MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA164P-20AQ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 25-10. 2-wire Serial Bus Requirements (Continued)
Notes:
8011O–AVR–07/10
Symbol
t
t
t
t
t
t
t
t
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
1. In ATmega164P/324P/644P, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100 kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega32 Two-wire Serial Interface operation. Other devices connected to the Two-wire
6. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater
7. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time require-
Serial Bus need only obey the general fSCL requirement.
than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.
ment will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega32 devices connected to the bus may
communicate at full speed (400 kHz) with other ATmega32 devices, as well as any other device with a proper tLOW accep-
tance margin.
Parameter
Hold Time (repeated) START Condition
Low Period of the SCL Clock
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
Figure 25-6. 2-wire Serial Bus Timing
SCL
SDA
t
SU;STA
t
HD;STA
t
t
of
LOW
f
f
SCL
SCL
f
f
f
f
f
f
f
f
f
f
f
f
f
f
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
Condition
≤ 100 kHz
> 100 kHz
t
HIGH
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
t
HD;DAT
(6)
(7)
t
LOW
ATmega164P/324P/644P
t
SU;DAT
250
100
Min
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
4.0
0.6
4.7
1.3
0
0
t
SU;STO
t
r
3.45
Max
0.9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
t
BUF
Units
µs
ns
µs
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