PIC16C72-04I/SO Microchip Technology, PIC16C72-04I/SO Datasheet - Page 51

• Manufacturer Part Number: PIC16C72-04I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C72-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.4.2
Master operation is supported in firmware using inter-
rupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared from a reset or when the SSP module is
disabled. The STOP (P) and START (S) bits will toggle
based on the START and STOP conditions. Control of
the I
bus is idle and both the S and P bits are clear.
In master operation, the SCL and SDA lines are manip-
ulated in firmware by clearing the corresponding
TRISC<4:3> bit(s). The output level is always low, irre-
spective of the value(s) in PORTC<4:3>. So when
transmitting data, a '1' data bit must have the
TRISC<4> bit set (input) and a '0' data bit must have
the TRISC<4> bit cleared (output). The same scenario
is true for the SCL line with the TRISC<3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master operation can be done with either the slave
mode idle (SSPM3:SSPM0 = 1011) or with the slave
active. When both master operation and slave modes
are used, the software needs to differentiate the
source(s) of the interrupt.
For more information on master operation, see AN554
- Software Implementation of I
TABLE 8-4
0Bh, 8Bh,
10Bh,18Bh
93h
94h
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Note 1: These bits are unimplemented, read as '0'.
Address
0Ch
8Ch
13h
14h
87h
1998 Microchip Technology Inc.
2
C bus may be taken when the P bit is set, or the
2: The SMP and CKE bits are implemented on the PIC16CR72 only. On the PIC16C72, these two bits are unimplemented,
MASTER OPERATION
Shaded cells are not used by SSP module in SPI mode.
read as '0'.
Name
INTCON
PIR1
PIE1
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPADD Synchronous Serial Port (I
SSPCON
SSPSTAT
TRISC
REGISTERS ASSOCIATED WITH I
PORTC Data Direction register
SMP
WCOL
Bit 7
GIE
(1)
(1)
(2)
2
C Bus Master .
SSPOV SSPEN
CKE
PEIE
ADIF
ADIE
Bit 6
(2)
Bit 5
T0IE
D/A
(1)
(1)
2
C mode) Address Register
Preliminary
INTE
Bit 4
CKP
(1)
(1)
P
2
SSPM3 SSPM2 SSPM1 SSPM0
SSPIF CCP1IF TMR2IF TMR1IF
SSPIE CCP1IE TMR2IE TMR1IE
C OPERATION
RBIE
Bit 3
S
8.4.3
In multi-master operation, the interrupt generation on
the detection of the START and STOP conditions
allows the determination of when the bus is free. The
STOP (P) and START (S) bits are cleared from a reset
or when the SSP module is disabled. The STOP (P)
and START (S) bits will toggle based on the START and
STOP conditions. Control of the I
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed an ACK pulse will be generated.
If arbitration was lost during the data transfer stage, the
device will need to re-transfer the data at a later time.
For more information on master operation, see AN578
- Use of the SSP Module in the of I
Environment .
Bit 2
T0IF
R/W
MULTI-MASTER OPERATION
PIC16C72 Series
Bit 1
INTF
UA
RBIF
Bit 0
BF
0000 000x
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
1111 1111
Value on
2
POR,
BOR
C bus may be taken
DS39016A-page 51
2
C Multi-Master
0000 000u
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
1111 1111
Value on
all other
resets