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DSPIC30F6012A-20E/PT
DSPIC30F6012A-20E/PT | |
|---|---|
| Manufacturer Part Number | DSPIC30F6012A-20E/PT |
| Description | IC DSPIC MCU/DSP 144K 64TQFP |
| Manufacturer | Microchip Technology |
| Series | dsPIC™ 30F |
| DSPIC30F6012A-20E/PT datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
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Specifications of DSPIC30F6012A-20E/PT | |||
|---|---|---|---|
| Program Memory Type | FLASH | Program Memory Size | 144KB (48K x 24) |
| Package / Case | 64-TFQFP | Core Processor | dsPIC |
| Core Size | 16-Bit | Speed | 20 MIPS |
| Connectivity | CAN, I²C, SPI, UART/USART | Peripherals | AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT |
| Number Of I /o | 52 | Eeprom Size | 4K x 8 |
| Ram Size | 8K x 8 | Voltage - Supply (vcc/vdd) | 2.5 V ~ 5.5 V |
| Data Converters | A/D 16x12b | Oscillator Type | Internal |
| Operating Temperature | -40°C ~ 125°C | Product | DSCs |
| Data Bus Width | 16 bit | Processor Series | DSPIC30F |
| Core | dsPIC | Maximum Clock Frequency | 20 MHz |
| Number Of Programmable I/os | 52 | Data Ram Size | 8 KB |
| Maximum Operating Temperature | + 125 C | Mounting Style | SMD/SMT |
| 3rd Party Development Tools | 52713-733, 52714-737, 53276-922, EWDSPIC | Development Tools By Supplier | PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011 |
| Minimum Operating Temperature | - 40 C | Package | 64TQFP |
| Device Core | dsPIC | Family Name | dsPIC30 |
| Maximum Speed | 20 MHz | Operating Supply Voltage | 3.3|5 V |
| Interface Type | CAN/I2C/SPI/UART | On-chip Adc | 16-chx12-bit |
| Number Of Timers | 5 | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
| For Use With | AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP | ||
DSPIC30F2011-20ISO PDF datasheetDSPIC30F2011-20IP PDF datasheet #2DSPIC30F6011A-30IPT PDF datasheet #3DSPIC30F6011A-30IPT PDF datasheet #4DSPIC30F6011A-30IPT PDF datasheet #5DSPIC30F6011A-30IPT PDF datasheet #6DSPIC30F6011A-30IPT PDF datasheet #7DSPIC30F6011A-30IPT PDF datasheet #8DSPIC30F6014A-20EPT PDF datasheet #9
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11.7
Writing Configuration Memory
The FOSC, FWDT, FBORPOR and FICD registers are
not erasable. It is recommended that all Configuration
registers be set to a default value after erasing program
memory. The FWDT, FBORPOR and FICD registers
can be set to a default all ‘1’s value by programming
0xFFFF to each register. Since these registers contain
unimplemented bits that read as ‘0’ the default values
shown in
Table 11-6
will be read instead of 0xFFFF.
The recommended default FOSC value is 0xC100,
which selects the FRC clock oscillator setting.
The FGS, FBS and FSS Configuration registers are
special since they enable code protection for the
device. For security purposes, once any bit in these
registers is programmed to ‘0’ (to enable some code
protection feature), it can only be set back to ‘1’ by
performing a Bulk Erase or Segment Erase as
described
in
Section 11.5
“Erasing
Memory in Normal-Voltage
Systems”. Programming
these bits from a ‘0’ to ‘1’ is not possible, but they may
be programmed from a ‘1’ to a ‘0’ to enable code
protection.
Table 11-7
shows the ICSP programming details for
clearing the Configuration registers. In Step 1, the
Reset vector is exited. In Step 2, the write pointer (W7)
is loaded with 0x0000, which is the original destination
address (in TBLPAG 0xF8 of program memory). In
Step 3, the NVMCON is set to program one Configura-
TABLE 11-7:
SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION
REGISTERS
Command
Data
(Binary)
(Hexadecimal)
Step 1: Exit the Reset vector.
0000
040100
GOTO 0x100
0000
040100
GOTO 0x100
0000
000000
NOP
Step 2: Initialize the write pointer (W7) for the TBLWT instruction.
0000
200007
MOV
Step 3: Set the NVMCON to program 1 Configuration register.
0000
24008A
MOV
0000
883B0A
MOV
Step 4: Initialize the TBLPAG register.
0000
200F80
MOV
0000
880190
MOV
Step 5: Load the Configuration register data to W6.
0000
2xxxx0
MOV
0000
000000
NOP
© 2010 Microchip Technology Inc.
tion register. In Step 4, the TBLPAG register is
initialized, to 0xF8, for writing to the Configuration
registers. In Step 5, the value to write to the each
Configuration register (0xFFFF) is loaded to W6. In
Step 6, the Configuration register data is written to the
write latch using the TBLWTL instruction. In Steps 7 and
8, the NVMCON is unlocked for programming and the
programming cycle is initiated, as described in
Section 11.4 “Flash Memory Programming in ICSP
Mode”. In Step 9, the internal PC is set to 0x100 as a
safety measure to prevent the PC from incrementing
into unimplemented memory. Lastly, Steps 3-9 are
repeated six times until all seven Configuration
registers are cleared.
TABLE 11-6:
DEFAULT CONFIGURATION
REGISTER VALUES
Address
Program
0xF80000
FOSC
0xF80002
FWDT
0xF80004
FBORPOR
0xF80006
FBS
0xF80008
FSS
0xF8000A
FGS
0xF8000C
FICD
Description
#0x0000, W7
#0x4008, W10
W10, NVMCON
#0xF8, W0
W0, TBLPAG
#<CONFIG_VALUE>, W0
Register
Default Value
0xC100
0x803F
0x87B3
0x310F
0x330F
0x0007
0xC003
DS70102K-page 43
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