IC DSPIC MCU/DSP 144K 64TQFP

 

DSPIC30F6012A-20E/PT

Manufacturer Part NumberDSPIC30F6012A-20E/PT
DescriptionIC DSPIC MCU/DSP 144K 64TQFP
ManufacturerMicrochip Technology
SeriesdsPIC™ 30F
DSPIC30F6012A-20E/PT datasheets

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Specifications of DSPIC30F6012A-20E/PT

Program Memory TypeFLASHProgram Memory Size144KB (48K x 24)
Package / Case64-TFQFPCore ProcessordsPIC
Core Size16-BitSpeed20 MIPS
ConnectivityCAN, I²C, SPI, UART/USARTPeripheralsAC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o52Eeprom Size4K x 8
Ram Size8K x 8Voltage - Supply (vcc/vdd)2.5 V ~ 5.5 V
Data ConvertersA/D 16x12bOscillator TypeInternal
Operating Temperature-40°C ~ 125°CProductDSCs
Data Bus Width16 bitProcessor SeriesDSPIC30F
CoredsPICMaximum Clock Frequency20 MHz
Number Of Programmable I/os52Data Ram Size8 KB
Maximum Operating Temperature+ 125 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
Minimum Operating Temperature- 40 CPackage64TQFP
Device CoredsPICFamily NamedsPIC30
Maximum Speed20 MHzOperating Supply Voltage3.3|5 V
Interface TypeCAN/I2C/SPI/UARTOn-chip Adc16-chx12-bit
Number Of Timers5Lead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP  
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Page 60/66

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APPENDIX A:
DEVICE-SPECIFIC
INFORMATION
A.1
Checksum Computation
The checksum computation is described in
“Checksum
Computation”.
Table A-1
16-bit computation can be made for each dsPIC30F
device. Computations for read code protection are
shown both enabled and disabled. The checksum
values assume that the Configuration registers are also
erased. However, when code protection is enabled, the
value of the FGS register is assumed to be 0x5.
TABLE A-1:
CHECKSUM COMPUTATION
Read Code
Device
Protection
dsPIC30F2010
Disabled
Enabled
dsPIC30F2011
Disabled
Enabled
dsPIC30F2012
Disabled
Enabled
dsPIC30F3010
Disabled
Enabled
dsPIC30F3011
Disabled
Enabled
dsPIC30F3012
Disabled
Enabled
dsPIC30F3013
Disabled
Enabled
dsPIC30F3014
Disabled
Enabled
dsPIC30F4011
Disabled
Enabled
dsPIC30F4012
Disabled
Enabled
dsPIC30F4013
Disabled
Enabled
dsPIC30F5011
Disabled
Enabled
dsPIC30F5013
Disabled
Enabled
dsPIC30F5015
Disabled
Enabled
Item Description:
SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory)
CFGB
= Configuration Block (masked) = Byte sum of ((FOSC&0xC10F) + (FWDT&0x803F) +
(FBORPOR&0x87B3) + (FBS&0x310F) + (FSS&0x330F) + (FGS&0x0007) + (FICD&0xC003))
DS70102K-page 60
A.2
dsPIC30F5011 and dsPIC30F5013
A.2.1
ICSP PROGRAMMING
The dsPIC30F5011 and dsPIC30F5013 processors
require that the FBS and FSS registers be programmed
Section 6.8
with 0x0000 before the device is chip erased. The steps
shows how this
to perform this action are shown in
A.2.2
ENHANCED ICSP PROGRAMMING
The dsPIC30F5011 and dsPIC30F5013 processors
require that the FBS and FSS registers be programmed
with 0x0000 using the PROGC command before the
ERASEB command is used to erase the chip.
Checksum Computation
CFGB+SUM(0:001FFF)
CFGB
CFGB+SUM(0:001FFF)
CFGB
CFGB+SUM(0:001FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:007FFF)
CFGB
CFGB+SUM(0:007FFF)
CFGB
CFGB+SUM(0:007FFF)
CFGB
CFGB+SUM(0:00AFFF)
CFGB
CFGB+SUM(0:00AFFF)
CFGB
CFGB+SUM(0:00AFFF)
CFGB
Table
11-4.
Value with
Erased
0xAAAAAA at 0x0
Value
and Last
Code Address
0xD406
0xD208
0x0404
0x0404
0xD406
0xD208
0x0404
0x0404
0xD406
0xD208
0x0404
0x0404
0xA406
0xA208
0x0404
0x0404
0xA406
0xA208
0x0404
0x0404
0xA406
0xA208
0x0404
0x0404
0xA406
0xA208
0x0404
0x0404
0xA406
0xA208
0x0404
0x0404
0x4406
0x4208
0x0404
0x0404
0x4406
0x4208
0x0404
0x0404
0x4406
0x4208
0x0404
0x0404
0xFC06
0xFA08
0x0404
0x0404
0xFC06
0xFA08
0x0404
0x0404
0xFC06
0xFA08
0x0404
0x0404
© 2010 Microchip Technology Inc.