MCU AVR 192K FLASH 64TQFP

ATXMEGA192D3-AU

Manufacturer Part NumberATXMEGA192D3-AU
DescriptionMCU AVR 192K FLASH 64TQFP
ManufacturerAtmel
SeriesAVR® XMEGA
ATXMEGA192D3-AU datasheets
 

Specifications of ATXMEGA192D3-AU

Core ProcessorAVRCore Size8/16-Bit
Speed32MHzConnectivityI²C, IrDA, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o50
Program Memory Size192KB (96K x 16)Program Memory TypeFLASH
Eeprom Size2K x 8Ram Size16K x 8
Voltage - Supply (vcc/vdd)1.6 V ~ 3.6 VData ConvertersA/D 16x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPController Family/seriesATXMEGA
No. Of I/o's50Eeprom Memory Size2KB
Ram Memory Size16KBCpu Speed32MHz
Rohs CompliantYesProcessor SeriesXMEGA
CoreAVRData Bus Width8 bit, 16 bit
Data Ram Size16 KBInterface TypeSPI, TWI, USART
Maximum Clock Frequency32 MHzNumber Of Programmable I/os50
Number Of Timers5Operating Supply Voltage2.5 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development ToolsEWAVR, EWAVR-BLMinimum Operating Temperature- 40 C
Operating Temperature Range- 40 C to + 85 CLead Free Status / RoHS StatusLead free / RoHS Compliant
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Features
High-performance, Low-power 8/16-bit
Non-volatile Program and Data Memories
– 64 KB - 256 KB of In-System Self-Programmable Flash
– 4 KB - 8 KB Boot Code Section with Independent Lock Bits
– 2 KB - 4 KB EEPROM
– 4 KB - 16 KB Internal SRAM
Peripheral Features
– Four-channel DMA Controller with support for external requests
– Eight-channel Event System
– Seven 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Capture channels
Three Timer/Counters with 2 Output Compare or Input Capture channels
High Resolution Extensions on all Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– Seven USARTs
IrDA Extension on 1 USART
– AES and DES Crypto Engine
– Two Two-wire Interfaces with dual address match (I
– Three SPI (Serial Peripheral Interfaces)
– 16-bit Real Time Counter with Separate Oscillator
– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters
– One Two-channel, 12-bit, 1 Msps Digital to Analog Converter
– Four Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interfaces
JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming
PDI (Program and Debug Interface) for programming, test and debugging
I/O and Packages
– 50 Programmable I/O Lines
– 64-lead TQFP
– 64-pad QFN
Operating Voltage
– 1.6 – 3.6V
Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
Typical Applications
Industrial control
Climate control
Factory automation
ZigBee
Building control
Motor control
Board control
Networking
White Goods
Optical
®
®
TM
Atmel
AVR
XMEGA
Microcontroller
2
C and SMBus compatible)
Hand-held battery applications
Power tools
HVAC
Metering
Medical Applications
8/16-bit
XMEGA A3
Microcontroller
ATxmega256A3
ATxmega192A3
ATxmega128A3
ATxmega64A3
8068T–AVR–12/10

ATXMEGA192D3-AU Summary of contents

  • Page 1

    ... ZigBee • • Building control Motor control • • Board control Networking • • White Goods Optical ® ® TM Atmel AVR XMEGA Microcontroller 2 C and SMBus compatible) • Hand-held battery applications • Power tools • HVAC • Metering • Medical Applications ...

  • Page 2

    ... ATxmega64A3- Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For packaging information, see ” ...

  • Page 3

    Pinout/Block Diagram Figure 2-1. Block diagram and pinout. INDEX CORNER PA3 1 PA4 2 PA5 3 PA6 4 PA7 5 PB0 6 PB1 7 PB2 8 PB3 9 PB4 10 PB5 11 PB6 12 PB7 13 GND 14 VCC ...

  • Page 4

    ... The Bootloader software in the Boot Flash section will continue to run while the Appli- cation Flash section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA power- ful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications ...

  • Page 5

    Block Diagram Figure 3-1. XMEGA A3 Block Diagram PA[0..7] PORT A (8) ACA ADCA AREFA VCC/10 Int. Ref. Tempref AREFB ADCB ACB PB[0..7]/ PORT B (8) JTAG DACB IRCOM 8068T–AVR–12/10 PR[0..1] XTAL1 XTAL2 Oscillator Circuits/ Clock Generation DATA BUS ...

  • Page 6

    ... The XMEGA application notes contain example code and show applied use of the modules and peripherals. The XMEGA Manual and Application Notes are available from http://www.atmel.com/avr. 5. Disclaimer For devices that are not available yet, typical values contained in this datasheet are based on simulations and characterization of other AVR XMEGA microcontrollers manufactured on the same process technology ...

  • Page 7

    AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 138 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in RAM • Stack Pointer accessible in I/O memory space • Direct ...

  • Page 8

    This concept enables instructions to be executed in every clock cycle. The program memory is In-System Re-programmable Flash memory. 6.3 Register File The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access ...

  • Page 9

    Memories 7.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section ...

  • Page 10

    In-System Programmable Flash Program Memory The XMEGA A3 devices contains On-chip In-System Programmable Flash memory for program storage, see Flash address location is 16 bits. The Program Flash memory space is divided into Application and Boot sections. Both sections ...

  • Page 11

    Data Memory The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one lin- ear address space, see devices in the family is identical and with empty, reserved memory space for smaller devices. Figure 7-2. ...

  • Page 12

    I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 general purpose ...

  • Page 13

    Production Signature Row The Production Signature Row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. The production signature row also contains a device ID that identify ...

  • Page 14

    Flash and EEPROM Page Size The Flash Program Memory and EEPROM data memory are organized in pages. The pages are word accessible for the Flash and byte accessible for the EEPROM. Table 7-2 on page 14 operations are performed ...

  • Page 15

    DMAC - Direct Memory Access Controller 8.1 Features • Allows High-speed data transfer – From memory to peripheral – From memory to memory – From peripheral to memory – From peripheral to peripheral • 4 Channels • From 1 ...

  • Page 16

    Event System 9.1 Features • Inter-peripheral communication and signalling with minimum latency • CPU and DMA independent operation • 8 Event Channels allows for signals to be routed at the same time • Events can be ...

  • Page 17

    Figure 9-1. The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Com- munication Module (IRCOM). Events can also be generated from software (CPU). All ...

  • Page 18

    System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: – 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32.768 kHz calibrated RC oscillator ...

  • Page 19

    Figure 10-1. Clock system overview Internal Oscillator Calibrated Internal Run-Time Calibrated Internal Oscillator Run-time Calibrated Internal Oscillator Each clock source is briefly described in the following sub-sections. 10.3 Clock Options 10.3.1 32 kHz Ultra Low Power Internal Oscillator The 32 ...

  • Page 20

    Crystal Oscillator The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter. 10.3.4 0.4 ...

  • Page 21

    Power Management and Sleep Modes 11.1 Features • 5 sleep modes – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction registers to disable clocks to unused peripherals 11.2 Overview The XMEGA A3 provides various ...

  • Page 22

    Extended Standby Mode Extended Standby mode is identical to Power-save mode with the exception that all enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces the wake-up time when external crystals ...

  • Page 23

    System Control and Reset 12.1 Features • Multiple reset sources for safe operation and device reset – Power-On Reset – External Reset – Watchdog Reset – Brown-Out Reset – PDI reset – Software reset • Asynchronous reset – No ...

  • Page 24

    Software reset The MCU can be reset by the CPU writing to a special I/O register through a timed sequence. 13. WDT - Watchdog Timer 13.1 Features • 11 selectable timeout periods, from 8s. • Two ...

  • Page 25

    PMIC - Programmable Multi-level Interrupt Controller 14.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts ...

  • Page 26

    Table 14-1. Reset and Interrupt Vectors (Continued) Program Address (Base Address) Source 0x040 NVM_INT_base 0x044 PORTB_INT_base 0x048 ACB_INT_base 0x04E ADCB_INT_base 0x056 PORTE_INT_base 0x05A TWIE_INT_base 0x05E TCE0_INT_base 0x06A TCE1_INT_base 0x072 SPIE_INT_vect 0x074 USARTE0_INT_base 0x07A USARTE1_INT_base 0x080 PORTD_INT_base 0x084 PORTA_INT_base 0x088 ACA_INT_base ...

  • Page 27

    I/O Ports 15.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events – Sense both edges – ...

  • Page 28

    Push-pull Figure 15-1. I/O configuration - Totem-pole 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input) 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input) 15.3.4 Bus-keeper The bus-keeper’s weak output produces the ...

  • Page 29

    Figure 15-4. I/O configuration - Totem-pole with bus-keeper 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down Figure 15-6. I/O configuration - Wired-AND with optional pull-up 8068T–AVR–12/10 DIRn OUTn INn OUTn INn INn OUTn XMEGA ...

  • Page 30

    Input sensing • Sense both edges • Sense rising edges • Sense falling edges • Sense low level Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure ...

  • Page 31

    T/C - 16-bits Timer/Counter with PWM 16.1 Features • Seven 16-bit Timer/Counters – Four Timer/Counters of type 0 – Three Timer/Counters of type 1 • Four Compare or Capture (CC) Channels in Timer/Counter 0 • Two Compare or Capture ...

  • Page 32

    Figure 16-1. Overview of a Timer/Counter and closely related peripherals Timer/Counter Base Counter Timer Period Compare/Capture Channel B Compare/Capture Channel A Comparator The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits (4x). This is ...

  • Page 33

    AWEX - Advanced Waveform Extension 17.1 Features • Output with complementary output from each Capture channel • Four Dead Time Insertion (DTI) Units, one for each Capture channel • 8-bit DTI Resolution • Separate High and Low Side Dead-Time ...

  • Page 34

    Hi-Res - High Resolution Extension 18.1 Features • Increases Waveform Generator resolution by 2-bits (4x) • Supports Frequency, single- and dual-slope PWM operation • Supports the AWEX when this is enabled and used for the same Timer/Counter 18.2 Overview ...

  • Page 35

    RTC - Real-Time Counter 19.1 Features • 16-bit Timer • Flexible Tick resolution ranging from 32.768 kHz • One Compare register • One Period register • Clear timer on Overflow or Compare Match • Overflow or ...

  • Page 36

    TWI - Two Wire Interface 20.1 Features • Two Identical TWI peripherals • Simple yet Powerful and Flexible Communication Interface • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space ...

  • Page 37

    SPI - Serial Peripheral Interface 21.1 Features • Three Identical SPI peripherals • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of ...

  • Page 38

    USART 22.1 Features • Seven Identical USART peripherals • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High-resolution Arithmetic Baud Rate Generator • Supports Serial ...

  • Page 39

    IRCOM - IR Communication Module 23.1 Features • Pulse modulation/demodulation for infrared communication • Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed ...

  • Page 40

    Crypto Engine 24.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) Crypto module • DES Instruction – Encryption and Decryption – Single-cycle DES instruction – Encryption/Decryption in 16 clock cycles per 8-byte block • ...

  • Page 41

    ADC - 12-bit Analog to Digital Converter 25.1 Features • Two ADCs with 12-bit resolution • 2 Msps sample rate for each ADC • Signed and Unsigned conversions • 4 result registers with individual input channel control for each ...

  • Page 42

    Figure 25-1. ADC overview Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.5 µs without any intervention by the application other than starting the conversion. The results ...

  • Page 43

    DAC - 12-bit Digital to Analog Converter 26.1 Features • One DAC with 12-bit resolution • Msps conversion rate for each DAC • Flexible conversion range • Multiple trigger sources • 1 continuous output or 2 ...

  • Page 44

    AC - Analog Comparator 27.1 Features • Four Analog Comparators • Selectable Power vs. Speed • Selectable hysteresis – mV • Analog Comparator output available on pin • Flexible Input Selection – All pins on ...

  • Page 45

    Figure 27-1. Analog comparator overview Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled 8068T–AVR–12/10 XMEGA A3 + Pin 0 output AC0 - Interrupts Interrupt sensitivity control + AC1 ...

  • Page 46

    Input Selection The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in Figure 27-1 on page ...

  • Page 47

    ... No limitation on debug/programming clock frequency versus system clock frequency 28.2 Overview The XMEGA A3 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s development tools - provides all the necessary functions to debug an application. It has support for program and data breakpoints, and can debug an application from C and high level language source code level, as well as assembler and disassembler level ...

  • Page 48

    ... The PDI physical interface uses one dedicated pin together with the Reset pin, and no general purpose pins are used. JTAG uses four general purpose pins on PORTB. The PDI is an Atmel proprietary protocol for communication between the microcontroller and Atmel’s or third party development tools. ...

  • Page 49

    Pinout and Pin Functions The pinout of XMEGA A3 is shown in pin may have several function. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate pin functions can ...

  • Page 50

    Communication functions SCL SDA SCLIN SCLOUT SDAIN SDAOUT XCKn RXDn TXDn SS MOSI MISO SCK 30.1.6 Oscillators, Clock and Event TOSCn XTALn CLKOUT EVOUT 30.1.7 Debug/System functions RESET PDI_CLK PDI_DATA TCK TDI TDO TMS 8068T–AVR–12/10 Serial Clock for TWI ...

  • Page 51

    Alternate Pin Functions The tables below show the main and alternate pin functions for all pins on each port. They also show which peripheral that makes use of or enables the alternate pin function. Table 30-1. Port A - ...

  • Page 52

    Table 30-3. Port C - Alternate functions PORT C PIN # INTERRUPT TCC0 PC0 16 SYNC OC0A PC1 17 SYNC OC0B PC2 18 SYNC/ASYNC OC0C PC3 19 SYNC OC0D PC4 20 SYNC PC5 21 SYNC PC6 22 SYNC PC7 23 ...

  • Page 53

    Table 30-6. Port F - Alternate functions PORT F PIN # INTERRUPT PF0 46 SYNC PF1 47 SYNC PF2 48 SYNC/ASYNC PF3 49 SYNC PF4 50 SYNC PF5 51 SYNC PF6 54 SYNC PF7 55 SYNC GND 52 VCC 53 ...

  • Page 54

    Bit Number 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 ...

  • Page 55

    Bit Number ...

  • Page 56

    Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A3. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual. Base Address 0x0000 0x0010 ...

  • Page 57

    Instruction Set Summary Mnemonics Operands Description ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry ADIW Rd, K Add Immediate to Word SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr ...

  • Page 58

    Mnemonics Operands Description CALL k call Subroutine RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register ...

  • Page 59

    Mnemonics Operands Description LD Rd, -Y Load Indirect and Pre-Decrement LDD Rd, Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ Load Indirect and Post-Increment LD Rd, -Z Load Indirect and Pre-Decrement LDD Rd, Z+q Load ...

  • Page 60

    Mnemonics Operands Description ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear SBI A, b Set Bit in I/O Register ...

  • Page 61

    Packaging information 33.1 64A PIN 0°~7° Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and ...

  • Page 62

    D Marked Pin TOP VIEW BOTTOM VIEW Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA ...

  • Page 63

    Electrical Characteristics All typical values are measured 25°C unless other temperature condition is given. All min- imum and maximum values are valid across operating temperature and voltage unless other conditions are given. 34.1 Absolute Maximum Ratings* ...

  • Page 64

    Table 34-1. Current Consumption (Continued) Symbol Parameter Power-save mode I CC Reset Current Consumption (2) Module current consumption RC32M RC32M w/DFLL RC2M RC2M w/DFLL RC32K PLL Watchdog normal mode BOD Continuous mode BOD Sampled mode Internal 1.00 V ref Temperature ...

  • Page 65

    Operating Voltage and Frequency Table 34-2. Symbol Clk The maximum CPU clock frequency of the XMEGA A3 devices is depending Figure 34-1 on page 65 Figure 34-1. Maximum Frequency vs. Vcc 8068T–AVR–12/10 Operating voltage and frequency ...

  • Page 66

    Flash and EEPROM Memory Characteristics Table 34-3. Endurance and Data Retention Symbol Parameter Flash EEPROM Table 34-4. Programming time Symbol Parameter Chip Erase Flash EEPROM Notes: 1. Programming is timed from the internal 2 MHz oscillator. 2. EEPROM is ...

  • Page 67

    ADC Characteristics Table 34-5. ADC Characteristics Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Gain Error Offset Error ADC ADC Clock frequency clk Conversion rate Conversion time (propagation delay) Sampling Time Conversion range AVCC Analog Supply Voltage ...

  • Page 68

    DAC Characteristics Table 34-7. DAC Characteristics Symbol Parameter INL Integral Non-Linearity DNL Differential Non-Linearity F Conversion rate clk AREF External reference voltage Reference input impedance Max output voltage Min output voltage Offset factory calibration accuracy Gain factory calibration accuracy ...

  • Page 69

    Brownout Detection Characteristics Table 34-10. Brownout Detection Characteristics Symbol Parameter BOD level 0 falling Vcc BOD level 1 falling Vcc BOD level 2 falling Vcc BOD level 3 falling Vcc BOD level 4 falling Vcc BOD level 5 falling ...

  • Page 70

    POR Characteristics Table 34-12. Power-on Reset Characteristics Symbol Parameter V POR threshold voltage falling V POT- V POR threshold voltage rising V POT+ 34.12 Reset Characteristics Table 34-13. Reset Characteristics Symbol Parameter Minimum reset pulse width Reset threshold voltage ...

  • Page 71

    Table 34-18. External 32.768kHz Crystal Oscillator and TOSC characteristics Symbol Parameter SF Safety factor Recommended crystal equivalent ESR/R 1 series resistance (ESR) Input capacitance between TOSC C IN_TOSC pins Note: 1. See Figure 34-2 on page 71 Figure 34-2. TOSC ...

  • Page 72

    Typical Characteristics 35.1 Active Supply Current Figure 35-1. Active Supply Current vs. Frequency Figure 35-2. Active Supply Current vs. Frequency 8068T–AVR–12/ 1.0 MHz External clock 25°C SYS 900 800 700 600 500 400 ...

  • Page 73

    Figure 35-3. Active Supply Current vs. Vcc Figure 35-4. Active Supply Current vs. VCC 8068T–AVR–12/ 1.0 MHz External Clock SYS 1000 900 800 700 600 500 400 300 200 100 0 1.6 1.8 2 2.2 2 ...

  • Page 74

    Figure 35-5. Active Supply Current vs. Vcc Figure 35-6. Active Supply Current vs. Vcc 8068T–AVR–12/ 2.0 MHz internal RC SYS 2000 1800 1600 1400 1200 1000 800 600 400 200 0 1.6 1.8 2 2.2 2 ...

  • Page 75

    Figure 35-7. Active Supply Current vs. Vcc 35.2 Idle Supply Current Figure 35-8. Idle Supply Current vs. Frequency 8068T–AVR–12/ MHz internal RC SYS 2.7 2.8 2 ...

  • Page 76

    Figure 35-9. Idle Supply Current vs. Frequency Figure 35-10. Idle Supply Current vs. Vcc 8068T–AVR–12/ MHz 25°C SYS Frequency [MHz] ...

  • Page 77

    Figure 35-11. Idle Supply Current vs. Vcc Figure 35-12. Idle Supply Current vs. Vcc 8068T–AVR–12/ 32.768 kHz internal RC SYS 1.6 1.8 2 2.2 2 2.0 MHz ...

  • Page 78

    Figure 35-13. Idle Supply Current vs. Vcc Figure 35-14. Idle Supply Current vs. Vcc 8068T–AVR–12/ MHz internal RC prescaled to 8 MHz SYS 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.6 1.8 2 2.2 2.4 f ...

  • Page 79

    Power-down Supply Current Figure 35-15. Power-down Supply Current vs. Temperature Figure 35-16. Power-down Supply Current vs. Temperature 8068T–AVR–12/10 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -40 -30 -20 - Temperature [°C] With WDT ...

  • Page 80

    Power-save Supply Current Figure 35-17. Power-save Supply Current vs. Temperature 35.5 Pin Pull-up Figure 35-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage 8068T–AVR–12/10 With WDT, sampled BOD and RTC from ULP enabled 3 2.5 2 1.5 1 0.5 ...

  • Page 81

    Figure 35-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage Figure 35-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage 8068T–AVR–12/ 3.0V CC 160 140 120 100 0 3.3V ...

  • Page 82

    Pin Output Voltage vs. Sink/Source Current Figure 35-21. I/O Pin Output Voltage vs. Source Current Figure 35-22. I/O Pin Output Voltage vs. Source Current 8068T–AVR–12/10 Vcc = 1.8V 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ...

  • Page 83

    Figure 35-23. I/O Pin Output Voltage vs. Source Current Figure 35-24. I/O Pin Output Voltage vs. Sink Current 8068T–AVR–12/10 Vcc = 3.3V 3.5 3 2.5 2 1.5 1 0.5 0 -20 -18 -16 -14 -12 Vcc = 1.8V 1.8 1.6 ...

  • Page 84

    Figure 35-25. I/O Pin Output Voltage vs. Sink Current Figure 35-26. I/O Pin Output Voltage vs. Sink Current 8068T–AVR–12/10 Vcc = 3.0V 0.7 0.6 0.5 0.4 0.3 0.2 0 Vcc = 3.3V 0.7 0.6 ...

  • Page 85

    Pin Thresholds and Hysteresis Figure 35-27. I/O Pin Input Threshold Voltage vs. V Figure 35-28. I/O Pin Input Threshold Voltage vs. V 8068T–AVR–12/ I/O Pin Read as “1” IH 2.5 2 1.5 1 0.5 0 1.6 1.8 ...

  • Page 86

    Figure 35-29. I/O Pin Input Hysteresis vs. V Figure 35-30. Reset Input Threshold Voltage vs. V 8068T–AVR–12/10 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2 2.2 2 I/O Pin Read as “1” IH 1.8 1.6 ...

  • Page 87

    Figure 35-31. Reset Input Threshold Voltage vs. V 35.8 Bod Thresholds Figure 35-32. BOD Thresholds vs. Temperature 8068T–AVR–12/ I/O Pin Read as “0” IL 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 ...

  • Page 88

    Figure 35-33. BOD Thresholds vs. Temperature 35.9 Oscillators and Wake-up Time 35.9.1 Internal 32.768 kHz Oscillator Figure 35-34. Internal 32.768 kHz Oscillator Calibration Step Size 8068T–AVR–12/10 BOD Level = 2.9V 3.06 3.04 3.02 3 2.98 2.96 2.94 2.92 2.9 -40 ...

  • Page 89

    Internal 2 MHz Oscillator Figure 35-35. Internal 2 MHz Oscillator CALA Calibration Step Size -0.10 % -0.20 % -0.30 % Figure 35-36. Internal 2 MHz Oscillator CALB Calibration Step Size 8068T–AVR–12/10 ° - ...

  • Page 90

    Internal 32 MHZ Oscillator Figure 35-37. Internal 32 MHz Oscillator CALA Calibration Step Size Figure 35-38. Internal 32 MHz Oscillator CALB Calibration Step Size 8068T–AVR–12/10 ° - 0.60 % 0.50 ...

  • Page 91

    Module current consumption Figure 35-39. AC current consumption vs. Vcc Figure 35-40. Power-up current consumption vs. Vcc 8068T–AVR–12/10 Low-power Mode 120 100 1.6 1.8 2 2.2 2.4 700 600 500 400 300 200 100 ...

  • Page 92

    Reset Pulsewidth Figure 35-41. Minimum Reset Pulse Width vs. Vcc 35.12 PDI Speed Figure 35-42. PDI Speed vs. Vcc 8068T–AVR–12/10 120 100 1.6 1.8 2 2.2 2 ...

  • Page 93

    Errata 36.1 ATxmega256A3 36.1.1 rev. E • Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously • VCC voltage scaler for AC is non-linear • ADC has increased INL error for some ...

  • Page 94

    Figure 36-1. Analog Comparator Voltage Scaler vs. Scalefac Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition ...

  • Page 95

    Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2 order to get a cor- rect result, or keep ADC voltage reference below 2 ADC Event on compare match non-functional ADC signalling ...

  • Page 96

    Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V Using the DAC with a reference voltage ...

  • Page 97

    Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken ...

  • Page 98

    TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/Workaround Clear the flag in software after address interrupt. ...

  • Page 99

    WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/Workaround Wait ...

  • Page 100

    B • Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously • VCC voltage scaler for AC is non-linear • ADC has increased INL error for some operating conditions • ADC ...

  • Page 101

    Figure 36-2. Analog Comparator Voltage Scaler vs. Scalefac Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition ...

  • Page 102

    Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2 order to get a cor- rect result, or keep ADC voltage reference below 2 ADC Event on compare match non-functional ADC signalling ...

  • Page 103

    Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V Using the DAC with a reference voltage ...

  • Page 104

    Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken ...

  • Page 105

    Problem fix/Workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 22. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will ...

  • Page 106

    Problem fix/Workaround None. 26. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing ...

  • Page 107

    A • Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously • ADC gain stage output range is limited to 2.4V • Sampled BOD in Active mode will cause noise when bandgap ...

  • Page 108

    Flash Power Reduction Mode can not be enabled when entering sleep mode If Flash Power Reduction Mode is enabled when a deep sleep mode, the device will only wake up on every fourth wake-up request. If Flash Power Reduction ...

  • Page 109

    Operating Frequency and Voltage Limitation To ensure correct operation, there is a limit on operating frequency and voltage. on page 109 Figure 36-3. Operating Frequnecy and Voltage Limitation Problem fix/Workaround None, avoid using the device outside these frequnecy and ...

  • Page 110

    ATxmega192A3, ATxmega128A3, ATxmega64A3 36.2.1 rev. E • Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously • VCC voltage scaler for AC is non-linear • ADC has increased INL error for some ...

  • Page 111

    Figure 36-4. Analog Comparator Voltage Scaler vs. Scalefac Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition ...

  • Page 112

    Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2 order to get a cor- rect result, or keep ADC voltage reference below 2 ADC Event on compare match non-functional ADC signalling ...

  • Page 113

    Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V Using the DAC with a reference voltage ...

  • Page 114

    Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken ...

  • Page 115

    TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/Workaround Clear the flag in software after address interrupt. ...

  • Page 116

    WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/Workaround Wait ...

  • Page 117

    B • Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously • VCC voltage scaler for AC is non-linear • ADC has increased INL error for some operating conditions • ADC ...

  • Page 118

    Figure 36-5. Analog Comparator Voltage Scaler vs. Scalefac Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition ...

  • Page 119

    Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2 order to get a cor- rect result, or keep ADC voltage reference below 2 ADC Event on compare match non-functional ADC signalling ...

  • Page 120

    Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V Using the DAC with a reference voltage ...

  • Page 121

    Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken ...

  • Page 122

    Problem fix/Workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 22. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will ...

  • Page 123

    Problem fix/Workaround None. 26. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing ...

  • Page 124

    ... E” . Added ERRATA “rev. B” . Updated ERRATA for ADC (ADC has increased INL error for some operating conditions). Updated the last page by Atmel new Brand Style Guide. Updated ”Errata” on page 93. Updated the Footnote 3 of ”Ordering Information” on page Updated Footnote 2 of ...

  • Page 125

    Added ...

  • Page 126

    37.9 8068L – 06/ 37.10 8068K – 02/09 1. 37.11 8068J – 12/08 1. 37.12 8068I – 11/08 1. 37.13 8068H – 10/08 1. 37.14 8068G – 09/ 8068T–AVR–12/10 ...

  • Page 127

    37.15 8068F – 08/ 37.16 8068E – 08/ 37.17 8068D – 06/08 1. 37.18 8068C – 06/ 37.19 8068B – 06/ ...

  • Page 128

    Updated ”Overview” on page 4, included the XMEGA A3 explanation text on page 6. Added XMEGA A3 Block Diagram, Figure 3-1 on page ...

  • Page 129

    Table of Contents Features ..................................................................................................... 1 Typical Applications ................................................................................ 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ................................................................................................... 4 4 Resources ................................................................................................. 6 5 Disclaimer ................................................................................................. 6 6 AVR CPU ................................................................................................... 7 7 Memories .................................................................................................. ...

  • Page 130

    Power Management and Sleep Modes ................................................. 21 12 System Control and Reset .................................................................... 23 13 WDT - Watchdog Timer ......................................................................... 24 14 PMIC - Programmable Multi-level Interrupt Controller ....................... 25 15 I/O Ports .................................................................................................. 27 16 T/C - 16-bits ...

  • Page 131

    RTC - Real-Time Counter ...................................................................... 35 20 TWI - Two Wire Interface ....................................................................... 36 21 SPI - Serial Peripheral Interface ............................................................ 37 22 USART ..................................................................................................... 38 23 IRCOM - IR Communication Module .................................................... 39 24 Crypto Engine ........................................................................................ 40 ...

  • Page 132

    Pinout and Pin Functions ...................................................................... 49 31 Peripheral Module Address Map .......................................................... 56 32 Instruction Set Summary ...................................................................... 57 33 Packaging information .......................................................................... 61 34 Electrical Characteristics ...................................................................... 63 35 Typical Characteristics .......................................................................... 72 XMEGA A3 iv 29.1Features ................................................................................................................48 ...

  • Page 133

    Wake-up Time ..............................................................................88 35.10Module current consumption ...............................................................................91 35.11Reset Pulsewidth .................................................................................................92 35.12PDI Speed ...........................................................................................................92 36 Errata ....................................................................................................... 93 36.1ATxmega256A3 .....................................................................................................93 36.2ATxmega192A3, ATxmega128A3, ATxmega64A3 .............................................110 37 Datasheet Revision History ................................................................ 124 37.18068T – 12/10 .....................................................................................................124 37.28068S – 09/10 .....................................................................................................124 37.38068R ...

  • Page 134

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...