ATXMEGA192D3-AU Atmel, ATXMEGA192D3-AU Datasheet - Page 115

MCU AVR 192K FLASH 64TQFP

ATXMEGA192D3-AU

Manufacturer Part Number
ATXMEGA192D3-AU
Description
MCU AVR 192K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheets

Specifications of ATXMEGA192D3-AU

Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
192KB (96K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
ATXMEGA
No. Of I/o's
50
Eeprom Memory Size
2KB
Ram Memory Size
16KB
Cpu Speed
32MHz
Rohs Compliant
Yes
Processor Series
XMEGA
Core
AVR
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
50
Number Of Timers
5
Operating Supply Voltage
2.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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8068T–AVR–12/10
22. TWI Transmit collision flag not cleared on repeated start
23. Clearing TWI Stop Interrupt Flag may lock the bus
24. TWI START condition at bus timeout will cause transaction to be dropped
25. TWI Data Interrupt Flag erroneously read as set
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the
hardware sets this flag due to a new address received, CLKHOLD is not cleared and the
SCL line is not released. This will lock the bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is
not IDLE, wait for the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
{
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
}
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
Problem fix/Workaround
None.
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
)
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
if ( !(COMMS_PORT.IN & PIN1_bm) )
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
break;
XMEGA A3
115

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