LH75411N0Q100C0;55 NXP Semiconductors, LH75411N0Q100C0;55 Datasheet - Page 25

• Manufacturer Part Number: LH75411N0Q100C0;55
• Description: IC ARM7 BLUESTREAK MCU 144LQFP
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH75411N0Q100C0;55

• Package / Case: 144-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 84MHz
• Connectivity: EBI/EMI, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LH75
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: JTAG, SPI, UART
• Maximum Clock Frequency: 84 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4330; 935285046557

System-on-Chip
Reset Generation
EXTERNAL RESETS
ARM7TDMI-S core:
• nPOR sets all internal registers to their default state
• nRESETIN sets all internal registers, except the
microcontroller Test Mode. When nPOR is released,
nRESETIN behaves during Reset as described
previously.
INTERNAL RESETS
• System Reset
• RTC Reset.
• An External Reset (a logic LOW signal on the exter-
• A signal from the internal Watchdog Timer
• A Soft Reset.
AHB Master Priority and Arbitration
AHB masters:
• ARM processor
• DMAC
• LCD Controller.
nent and cannot change.
Preliminary data sheet
1 (Highest)
2
3 (Lowest)
PRIORITY
when asserted. It is used as a Power-On Reset.
JTAG circuitry, to their default state when asserted.
nal nRESETIN or nPOR input pin)
Two external signals generate resets to the
When nPOR is asserted, nRESETIN defines the
There are two types of Internal Resets generated:
System and RTC Resets are asserted by:
The reset latency depends on the PLL lock state.
The LH75401/LH75411 microcontrollers have three
Each AHB master has a priority level that is perma-
Table 6. Bus Master Priority
Color LCDC (LH75401 and LH75411)
DMAC
ARM7TDMI-S Core (Default)
BUS MASTER PRIORITY
NXP Semiconductors
Rev. 01 — 16 July 2007
Memory Interface Architecture
following data-path management resources on chip:
• AHB and APB data buses
• 16 kB of zero-wait-state TCM SRAM accessible via
• 16 kB of internal SRAM accessible via processor,
• A Static Memory Controller (SMC) that controls
• A 4-stream general-purpose DMAC.
memory-mapped. This memory map partition has three
views, based on the setting of the REMAP bits in the
Reset, Clock, and Power Controller (RCPC).
dividing of the segments into sections. The external
memory segment is divided into eight 64 MB sections,
of which the first four are used, each having a chip
select associated with it. Access to any of the last four
sections does not result in an external bus access and
does not cause a memory abort. The peripheral regis-
ter segment is divided into 4 kB peripheral sections, 21
of which are assigned to peripherals.
0xE0000000 -
0xFFFBFFFF
0xA0000000
0xC0000000
0x00000000
0x20000000
0x40000000
0x60000000
0x80000000
ADDRESS
processor
DMAC, and LCDC
access to external memory
The LH75401/LH75411 microcontrollers provide the
All external and internal system resources are
The second partitioning of memory space is the
Table 7. Memory Mapping
REMAP = 00
(DEFAULT)
TCM SRAM
Reserved
Reserved
Reserved
Reserved
External
Memory
External
Memory
Internal
SRAM
REMAP = 01 REMAP = 10
TCM SRAM
Reserved
Reserved
Reserved
Reserved
External
Memory
Internal
Internal
SRAM
SRAM
LH75401/LH75411
TCM SRAM
TCM SRAM
Reserved
Reserved
Reserved
Reserved
External
Memory
Internal
SRAM
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