LPC2194HBD64/01,15 NXP Semiconductors, LPC2194HBD64/01,15 Datasheet
LPC2194HBD64/01,15
Specifications of LPC2194HBD64/01,15
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LPC2194HBD64/01-S
LPC2194HBD64/01-S
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LPC2194HBD64/01,15 Summary of contents
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LPC2194 Single-chip 16/32-bit microcontroller; 256 kB ISP/IAP flash with 10-bit ADC and CAN Rev. 05 — 10 December 2007 1. General description The LPC2194 is based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with ...
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... NXP Semiconductors 2.2 Key features common for all devices I 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package on-chip SRAM and 256 kB on-chip flash program memory. 128-bit wide interface/accelerator enables high speed 60 MHz operation. I In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software ...
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... NXP Semiconductors 4. Block diagram LPC2194 P0[30:27], HIGH-SPEED P0[25:0] (3) GPI/O 46 PINS TOTAL P1[31:16] ARM7 LOCAL BUS INTERNAL SRAM CONTROLLER 16 kB SRAM EXTERNAL (1) EINT[3:0] INTERRUPTS (1) 4 CAP0 CAPTURE/ (1) 4 CAP1 COMPARE (1) 4 MAT0 TIMER 0/TIMER 1 (1) 4 MAT1 (1) A/D CONVERTER AIN[3:0] P0[30:27], GENERAL P0[25:0] ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning P0[21]/PWM5/RD3/CAP1[3] 1 P0[22]/TD3/CAP0[0]/MAT0[ P0[23]/RD2 P1[19]/TRACEPKT3 4 P0[24]/TD2 DDA(3V3) P1[18]/TRACEPKT2 8 P0[25]/RD1 9 10 TD1 P0[27]/AIN0/CAP0[1]/MAT0[1] 11 P1[17]/TRACEPKT1 12 P0[28]/AIN1/CAP0[2]/MAT0[ P0[29]/AIN2/CAP0[3]/MAT0[3] P0[30]/AIN3/EINT3/CAP0[0] 15 P1[16]/TRACEPKT0 16 Fig 2. Pin configuration ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin P0[0] to P0[31] P0[0]/TXD0/ 19 PWM1 P0[1]/RXD0/ 21 PWM3/EINT0 P0[2]/SCL/ 22 CAP0[0] P0[3]/SDA/ 26 MAT0[0]/EINT1 P0[4]/SCK0/ 27 CAP0[1] P0[5]/MISO0/ 29 MAT0[1] P0[6]/MOSI0/ 30 CAP0[2] P0[7]/SSEL0/ 31 PWM2/EINT2 P0[8]/TXD1/ 33 PWM4 P0[9]/RXD1/ ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin P0[14]/DCD1/ 41 EINT1 P0[15]/RI1/EINT2 45 P0[16]/EINT0/ 46 MAT0[2]/CAP0[2] P0[17]/CAP1[2]/ 47 SCK1/MAT1[2] P0[18]/CAP1[3]/ 53 MISO1/MAT1[3] P0[19]/MAT1[2]/ 54 MOSI1/CAP1[2] P0[20]/MAT1[3]/ 55 SSEL1/EINT3 P0[21]/PWM5/ 1 RD3/CAP1[3] P0[22]/TD3/ 2 CAP0[0]/MAT0[0] P0[23]/RD2 3 P0[24]/TD2 5 P0[25]/RD1 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin P0[30]/AIN3/ 15 EINT3/CAP0[0] P1[0] to P1[31] P1[16]/ 16 TRACEPKT0 P1[17]/ 12 TRACEPKT1 P1[18]/ 8 TRACEPKT2 P1[19]/ 4 TRACEPKT3 P1[20]/ 48 TRACESYNC P1[21]/ 44 PIPESTAT0 P1[22]/ 40 PIPESTAT1 P1[23]/ 36 PIPESTAT2 P1[24]/ 32 TRACECLK P1[25]/EXTIN0 28 P1[26]/RTCK 24 P1[27]/TDO 64 P1[28]/TDI 60 P1[29]/TCK ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin V 59 SSA V 58 SSA(PLL) V 17, 49 DD(1V8 DDA(1V8) V 23, 43, 51 DD(3V3 DDA(3V3) [1] SSP interface available on LPC2194/01 only. LPC2194_5 Product data sheet Type Description I analog ground reference. This should nominally be the same voltage as V but should be isolated to minimize noise and error. ...
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... NXP Semiconductors 6. Functional description Details of the LPC2194 systems and peripheral functions are described in the following sections. 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers ...
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... NXP Semiconductors ISP flash erase command can be executed at any time (no matter whether the CRP off). Removal of CRP is achieved by erasure of full on-chip user flash. With the CRP off, full access to the chip via the JTAG and/or ISP is restored. 6.3 On-chip SRAM On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed as 8 bit, 16 bit, and 32 bit ...
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... NXP Semiconductors Fig 3. LPC2194 memory map 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... NXP Semiconductors Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. ...
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... NXP Semiconductors Table 3. Block System Control ADC CAN [1] SSP interface available on LPC2194/01 only. 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals ...
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... NXP Semiconductors • Ports are accessible via either the legacy group of registers (GPIOs) or the group of registers providing accelerated port access (Fast GPIOs). 6.8 10-bit ADC The LPC2194 each contain a single 10-bit successive approximation ADC with four multiplexed channels. 6.8.1 Features • ...
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... NXP Semiconductors • Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs. • UART1 is equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). 6.10.2 UART features available in LPC2194/01 only Compared to previous LPC2000 microcontrollers, UARTs in LPC2194/01 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz ...
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... NXP Semiconductors 6.12 SPI serial I/O controller The LPC2194 each contain two SPIs. The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. ...
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... NXP Semiconductors 6.14.1 Features • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. • Timer or external event counter operation • Four 32-bit capture channels per timer that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. • ...
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... NXP Semiconductors • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal pre-scaler. • Selectable time period from (T T cy(PCLK) 6.16 Real-time clock The RTC is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode) ...
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... NXP Semiconductors With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge) ...
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... NXP Semiconductors produce the output clock. Since the minimum output divider value insured that the PLL output has duty cycle. The PLL is turned off and bypassed following a chip Reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source ...
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... NXP Semiconductors CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. Remark: Devices without the /00 or /01 suffixes have only a security level equivalent to CRP2 available. 6.18.5 External interrupt inputs The LPC2194 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions ...
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... NXP Semiconductors when an application does not require any peripherals to run at the full processor rate. Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode. 6.19 Emulation and debugging The LPC2194 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution ...
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... NXP Semiconductors 6.19.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC (Debug Communications Channel), which is present in the EmbeddedICE logic. The LPC2194 contain a specifi ...
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... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage (3.3 V) DDA(3V3) V analog input voltage IA V input voltage I I supply current DD I ground current ...
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... NXP Semiconductors 8. Static characteristics Table 5. Static characteristics +125 C for industrial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage DDA(3V3) (3.3 V) Standard port pins, RESET, RTCK I LOW-level input current IL I HIGH-level input current ...
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... NXP Semiconductors Table 5. Static characteristics +125 C for industrial applications, unless otherwise specified. amb Symbol Parameter I Power-down mode supply DD(pd) current Power consumption LPC2194/01 I active mode supply DD(act) current I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current 2 I C-bus pins ...
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... NXP Semiconductors [4] Including voltage on outputs in 3-state mode. [5] V supply voltages must be present. DD(3V3) [6] 3-state outputs go into 3-state mode when V [7] Accounts for 100 mV voltage drop in all supply lines. [8] Only allowed for a short time period. [9] Minimum condition for V = 4.5 V, maximum condition for V I [10] Applies to P1[25:16] ...
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... NXP Semiconductors Table 6. ADC static characteristics +125 C unless otherwise specified; ADC frequency 4.5 MHz. DDA amb Symbol Parameter V analog input voltage IA C analog input ia capacitance E differential linearity D error E integral non-linearity L(adj) E offset error O E gain error G E absolute error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 4. ADC characteristics LPC2194_5 Product data sheet ...
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... NXP Semiconductors 8.1 Power consumption measurements for LPC2194/01 The power consumption measurements represent typical values for the given conditions. The peripherals were enabled through the PCONP register, but for these measurements, the peripherals were not configured to run. Peripherals were disabled through the PCONP register ...
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... NXP Semiconductors 45 I DD(act) 60 MHz (mA MHz MHz 5 1.65 Test conditions: Active mode entered executing code from on-chip flash; PCLK = Temp = 25 C; core voltage 1.8 V; all peripherals disabled. Fig 7. Typical LPC2194/01 I DD(act) 15.0 I DD(idle) (mA) 10.0 5.0 0 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = ...
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... NXP Semiconductors 15.0 I DD(idle) (mA) 10.0 5.0 0.0 1.65 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals enabled. amb Fig 9. Typical LPC2194/01 I DD(idle) 8.0 I DD(idle) (mA) 6.0 4.0 2.0 0.0 1.65 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = Temp = 25 C ...
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... NXP Semiconductors 500 I DD(pd 400 300 200 100 0 -40 -25 -10 Test conditions: Power-down mode entered executing code from on-chip flash. Fig 11. Typical LPC2194/01 core power-down current DD(act) (mA -40 -25 -10 Test conditions: code executed from on-chip flash; PCLK = core voltage 1.8 V; all peripherals disabled. ...
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... NXP Semiconductors 7.0 I DD(idle) (mA) 6.0 5.0 4.0 3.0 2.0 1.0 -40 -25 -10 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals disabled. Fig 13. Typical LPC2194/01 I DD(idle) Table 7. Core voltage 1 Peripheral Timer0 Timer1 UART0 UART1 PWM0 ...
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... NXP Semiconductors 9. Dynamic characteristics Table 8. Dynamic characteristics +125 C for industrial applications; V amb Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time CLCH t clock fall time CHCL Port pins (except P0[2] and P0[3]) ...
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... NXP Semiconductors 10. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors 11. Abbreviations Table 9. Acronym ADC AMBA APB CAN CPU DCC FIFO GPIO I/O JTAG PLL PWM RAM SPI SRAM SSI SSP TTL UART LPC2194_5 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Controller Area Network ...
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... NXP Semiconductors 12. Revision history Table 10. Revision history Document ID Release date LPC2194_5 20071210 • Modifications: Type number LPC2194HBD64/01 has been added. • Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP) and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) added. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features brought by LPC2194/01 devices . 1 2.2 Key features common for all devices . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 9 6.1 Architectural overview 6.2 On-chip fl ...