ST7FLITEU09M6TR STMicroelectronics, ST7FLITEU09M6TR Datasheet - Page 75

• Manufacturer Part Number: ST7FLITEU09M6TR
• Description: MCU 8BIT SGL VOLT FLASH SO-8
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU09M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: No

ST7LITEU05 ST7LITEU09
Note:
Note:
Caution:
PWM frequency and duty cycle
The PWM signal frequency (f
value.
f
Following the above formula, if f
register value = 4094), and the minimum value is 2 kHz (ATR register value = 0).
The maximum value of ATR is 4094 because it must be lower than the DCR value which
must be 4095 in this case.
At reset, the counter starts counting from 0.
Software must write the duty cycle value in the DCR0H and DCR0L preload registers. The
DCR0H register must be written first. See caution below.
When a upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter,
the preloaded Duty cycle value is transferred to the Duty Cycle register and the PWM0
signal is set to a high level. When the upcounter matches the DCRx value the PWM0 signals
is set to a low level. To obtain a signal on the PWM0 pin, the contents of the DCR0 register
must be greater than the contents of the ATR register.
The polarity bit can be used to invert the output signal.
The maximum available resolution for the PWM0 duty cycle is:
Resolution = 1 / (4096 - ATR)
To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum
resolution and assuming that DCR=ATR, a 0% or 100% duty cycle can be obtained by
changing the polarity .
As soon as the DCR0H is written, the compare function is disabled and will start only when
the DCR0L value is written. If the DCR0H write occurs just before the compare event, the
signal on the PWM output may not be set to a low level. In this case, the DCRx register
should be updated just after an OVF event. If the DCR and ATR values are close, then the
DCRx register shouldbe updated just before an OVF event, in order not to miss a compare
event and to have the right signal applied on the PWM output.
Figure 38. PWM function
PWM
= f
COUNTER
AUTO-RELOAD
DUTY CYCLE
REGISTER
REGISTER
WITH OE0=1
AND OP0=0
WITH OE0=1
AND OP0=1
(DCR0)
(ATR)
4095
000
/ (4096 - ATR)
PWM
CPU
) is controlled by the counter period and the ATR register
is 8 MHz, the maximum value of f
PWM
On-chip peripherals
is 4 MHz (ATR
t
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