ST7FLIT10BY0M6 STMicroelectronics, ST7FLIT10BY0M6 Datasheet - Page 137

• Manufacturer Part Number: ST7FLIT10BY0M6
• Description: IC MCU 8BIT 2K FLASH 16-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLIT10BY0M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Processor Series: ST7FLIT1x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 107. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
4. Depends on f
OSC
t
t
w(SCKH)
t
w(SCKL)
Symbol
1/t
t
t
t
dis(SO)
t
t
t
t
t
t
su(SS)
t
su(MI)
t
h(MO)
su(SI)
a(SO)
h(SO)
v(MO)
t
t
h(SS)
v(SO)
h(MI)
h(SI)
r(SCK)
f(SCK)
f
MISO
MOSI
c(SCK)
, and T
SCK
SS
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
1)
1)
1)
OUTPUT
INPUT
1)
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
CPU
see note 2
. For example, if f
t
a(SO)
t
su(SS)
t
su(SI)
Parameter
4)
CPU
t
t
MSB IN
w(SCKH)
w(SCKL)
MSB OUT
=8MHz, then T
t
t
h(SI)
c(SCK)
t
DD
v(SO)
DD
CPU
,
Master
f
Slave
f
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable
edge)
CPU
CPU
BIT6 OUT
and 0.7xV
= 1/f
=8MHz
=8MHz
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Conditions
3)
CPU
DD
=125ns and t
BIT1 IN
.
t
h(SO)
su(SS)
(4 x T
t
t
r(SCK)
f(SCK)
f
CPU
see I/O port pin description
0.0625
=550ns
Min
CPU
120
100
100
100
100
100
90
0
0
0
0
LSB IN
/128
) + 50
LSB OUT
t
h(SS)
ST7LITE1xB
f
f
CPU
CPU
Max
120
240
120
120
2
4
/4
/2
t
dis(SO)
137/159
note 2
Unit
see
MHz
ns