ST7FLIT10BF1B6 STMicroelectronics, ST7FLIT10BF1B6 Datasheet - Page 24

• Manufacturer Part Number: ST7FLIT10BF1B6
• Description: IC MCU 8BIT 4K FLASH 20-DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLIT10BF1B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ST7FLIT1x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7LITE1xB
– The x8 PLL is intended for operation with V
Refer to
tion.
If the PLL is disabled and the RC oscillator is ena-
bled, then f
If both the RC oscillator and the PLL are disabled,
f
Figure 13. PLL Output Frequency Timing
Diagram
When the PLL is started, after reset or wake up
from Halt mode or AWUFH mode, it outputs the
clock after a delay of t
24/159
1
OSC
the 3.3V to 5.5V range
4/8 x
input
freq.
is driven by the external clock.
t
STARTUP
Section 15.1
OSC =
t
LOCK
1MHz.
STARTUP
for the option byte descrip-
1)
LOCKED bit set
t
.
STAB
DD
t
in
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACC
a stabilization time of t
13.3.5 Internal RC Oscillator and
Refer to
of the LOCKED bit in the SICSR register.
Note 1:
It is possible to obtain f
5.5V range with internal RC and PLL enabled by
selecting 1MHz RC and x8 PLL and setting the
PLLdiv2 bit in the PLLTST register (see
7.6.4 on page
section 7.6.4 on page 35
35).
OSC
STAB
= 4MHz in the 3.3V to
(see
PLL
) is reached after
PLL)
for a description
Figure 13
section
and