ST7FLITE09M6TR STMicroelectronics, ST7FLITE09M6TR Datasheet - Page 102

• Manufacturer Part Number: ST7FLITE09M6TR
• Description: IC MCU 8BIT FLASH 16SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE09M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC
• Processor Series: ST7FLITE0x
• Core: ST7
• Data Bus Width: 8 bit
• Development Tools By Supplier: ST7FLIT0-IND/USB, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE0xY0, ST7LITESxY0
13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 78. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
4. Depends on f
102/124
1
OSC
t
t
w(SCKH)
t
w(SCKL)
1/t
Symbol
t
t
t
t
t
dis(SO)
t
t
t
t
su(SS)
t
su(MI)
t
v(MO)
h(MO)
su(SI)
a(SO)
h(SO)
t
t
h(SS)
v(SO)
f
h(MI)
h(SI)
r(SCK)
f(SCK)
SCK =
MISO
MOSI
c(SCK)
, and T
SS
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
1)
1)
1)
OUTPUT
INPUT
1)
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
CPU
see note 2
. For example, if f
t
a(SO)
Parameter
t
su(SS)
t
su(SI)
4)
CPU
t
t
MSB IN
w(SCKH)
w(SCKL)
MSB OUT
=8MHz, then T
t
t
h(SI)
c(SCK)
Master
Slave
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable edge)
t
DD
v(SO)
DD
CPU
,
BIT6 OUT
and 0.7xV
= 1/f
Conditions
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
3)
CPU
DD
=125ns and t
BIT1 IN
f
f
.
CPU
CPU
t
h(SO)
=8MHz
=8MHz
su(SS)
t
t
r(SCK)
f(SCK)
f
T
CPU
CPU
0.0625
=175ns
see I/O port pin description
Min
120
100
100
100
100
100
90
/128 =
0
0
0
0
LSB IN
+ 50
LSB OUT
t
h(SS)
f
f
CPU
CPU
Max
120
240
120
120
2
4
/4 =
/2 =
t
dis(SO)
Unit
MHz
ns
note 2
see