ST7FLITES5Y0M6 STMicroelectronics, ST7FLITES5Y0M6 Datasheet - Page 55

MCU 8BIT 1K FLASH 16SOIC

ST7FLITES5Y0M6

Manufacturer Part Number
ST7FLITES5Y0M6
Description
MCU 8BIT 1K FLASH 16SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLITES5Y0M6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (3.9mm Width)
Processor Series
ST7FLITESx
Core
ST7
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLIT0-IND/USB, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-4863

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12-BIT AUTORELOAD TIMER (Cont’d)
Figure 36. PWM Signal Example
Output Compare Mode
To use this function, the OE bit must be 0, other-
wise the compare is done with the shadow register
instead of the DCRx register. Software must then
write a 12-bit value in the DCR0H and DCR0L reg-
isters. This value will be loaded immediately (with-
out waiting for an OVF event).
The DCR0H must be written first, the output com-
pare function starts only when the DCR0L value is
written.
When the 12-bit upcounter (CNTR) reaches the
value stored in the DCR0H and DCR0L registers,
the CMPF0 bit in the PWM0CSR register is set
and an interrupt request is generated if the CMPIE
bit is set.
Note: The output compare function is only availa-
ble for DCRx values other than 0 (reset value).
Caution: At each OVF event, the DCRx value is
written in a shadow register, even if the DCR0L
value has not yet been written (in this case, the
shadow register will contain the new DCR0H value
and the old DCR0L value), then:
– If OE=1 (PWM mode): the compare is done be-
– if OE=0 (OCMP mode): the compare is done be-
tween the timer counter and the shadow register
(and not DCRx)
tween the timer counter and DCRx. There is no
PWM signal.
DCR0=FFEh
COUNTER
f
COUNTER
FFDh
FFEh
ATR= FFDh
FFFh
FFDh
The compare between DCRx or the shadow regis-
ter and the timer counter is locked until DCR0L is
written.
11.2.4 Low Power Modes
11.2.5 Interrupts
Notes:
1. The interrupt events are connected to separate
interrupt vectors (see Interrupts chapter).
They generate an interrupt if the enable bit is set in
the ATCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
2. only if CK0=1and CK1=0
Mode
SLOW
WAIT
ACTIVE-HALT
HALT
Overflow
Event
CMP Event
Interrupt
Event
FFEh
1)
CMPFx CMPIE Yes
Event
Flag
OVF
ST7LITE0xY0, ST7LITESxY0
FFFh
Description
The input frequency is divided
by 32
No effect on AT timer
AT timer halted except if CK0=1,
CK1=0 and OVFIE=1
AT timer halted
Control
Enable
OVFIE
Bit
FFDh
from
Wait
Exit
Yes
from
Exit
Halt
FFEh
No
No
Active-
Yes
from
Exit
Halt
t
No
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2)
1

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