ST72F623F2M1 STMicroelectronics, ST72F623F2M1 Datasheet - Page 48

• Manufacturer Part Number: ST72F623F2M1
• Description: IC MCU 8BIT LS 8K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F623F2M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-2114-5

ST7262xxx
PWM AUTO-RELOAD TIMER (Cont’d)
Input capture function
This mode allows the measurement of external
signal pulse widths through ICRx registers.
Each input capture can generate an interrupt inde-
pendently on a selected input signal transition.
This event is flagged by a set of the corresponding
CFx bits of the Input Capture Control/Status regis-
ter (ICCSR).
These input capture interrupts are enabled
through the CIEx bits of the ICCSR register.
The active transition (falling or rising edge) is soft-
ware programmable through the CSx bits of the
ICCSR register.
The read only input capture registers (ICRx) are
used to latch the auto-reload counter value when a
transition is detected on the ARTICx pin (CFx bit
set in ICCSR register). After fetching the interrupt
vector, the CFx flags can be read to identify the in-
terrupt source.
Note: After a capture detection, data transfer in
the ICRx register is inhibited until the ARTICCSR
register is read (clearing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
set). This means, the ARTICCSR register has to
be read at each capture event to clear the CFx
flag.
The timing resolution is given by auto-reload coun-
ter cycle time (1/f
Figure 37. Input Capture Timing Diagram
48/139
ICRx REGISTER
ARTICx PIN
COUNTER
CFx FLAG
COUNTER
f
COUNTER
).
01h
02h
xxh
03h
Doc ID 6996 Rev 5
04h
During HALT mode, input capture is inhibited (the
ICRx is never re-loaded) and only the external in-
terrupt capability can be used.
External interrupt capability
This mode allows the Input capture capabilities to
be used as external interrupt sources.
The edge sensitivity of the external interrupts is
programmable (CSx bit of ICCSR register) and
they are independently enabled through CIEx bits
of the ICCSR register. After fetching the interrupt
vector, the CFx flags can be read to identify the in-
terrupt source.
The interrupts are synchronized on the counter
clock rising edge
During HALT mode, the external interrupts can still
be used to wake up the micro (if CIEx bit is set).
Figure 36. ART External Interrupt
ARTICx PIN
CFx FLAG
f
COUNTER
05h
INTERRUPT
04h
06h
(Figure
07h
36).
t
INTERRUPT
t