Z8F4822AR020SG Zilog, Z8F4822AR020SG Datasheet - Page 164

• Manufacturer Part Number: Z8F4822AR020SG
• Description: IC ENCORE MCU FLASH 48K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F4822AR020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z8F482x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4271; Z8F4822AR020SG

PS019921-0308
S
Slave Address
Read Transaction with a 10-Bit Address
1st 7 bits
4. The I
5. The I
6. If the I
7. The I
8. The I
9. Software responds by reading the I
10. If there are more bytes to transfer, return to
11. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I
12. Software responds by setting the STOP bit of the I
13. A STOP condition is sent to the I
Figure 32
regions indicate data transferred from the I
indicate data transferred from the slaves to the I
The first seven bits transmitted in the first byte are
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
Figure 32. Receive Data Format for a 10-Bit Addressed Slave
next high period of SCL, the I
Continue with
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status register, ACK bit is cleared). Software responds to the Not
Acknowledge interrupt by setting the STOP bit and clearing the TXI bit. The I
Controller sends the STOP condition on the bus and clears the STOP and NCKI bits.
The transaction is complete (ignore the following steps).
I
byte), else it sends an Acknowledge.
is only one more byte to receive, set the NAK bit of the I
Controller.
2
C Controller sends a Not Acknowledge to the I
W=0 A
2
2
2
2
C Controller shifts in the byte of data from the I
displays the read transaction format for a 10-bit addressed slave. The shaded
C Controller sends the START condition.
C Controller shifts the address and read bit out the SDA signal.
C Controller asserts the Receive interrupt (RDRF bit set in the Status register).
2
C slave acknowledges the address by pulling the SDA signal Low during the
Slave Address
step
2nd Byte
7.
2
C Controller sets the ACK bit in the I
A S
2
C slave, the STOP and NCKI bits are cleared.
2
C Data register which clears the RDRF bit. If there
2
Slave Address
C Controller to slaves and unshaded regions
1st 7 bits
2
step
C Controller.
11110XX
7.
2
C slave if the NAK bit is set (last
2
Z8 Encore! XP
C Control register.
2
C slave on the SDA signal. The
. The two bits
2
R=1 A Data A Data A P
C Control register.
Product Specification
2
®
C Status register.
F64XX Series
XX
I2C Controller
are the two
2
C
2
C
150