Z8F4822AR020SG Zilog, Z8F4822AR020SG Datasheet - Page 50

• Manufacturer Part Number: Z8F4822AR020SG
• Description: IC ENCORE MCU FLASH 48K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F4822AR020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z8F482x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4271; Z8F4822AR020SG

DMA0 Control
DMA0CTL (FB0H - Read/Write)
DMA0 I/O Address
DMA0IO (FB1H - Read/Write)
PS019921-0308
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Request Trigger Source Select
000 = Timer 0
001 = Timer 1
010 = Timer 2
011 = Timer 3
100 = UART0 Received Data
register
101 = UART1 Received Data
register
110 = I2C receiver contains valid
data
111 = Reserved
Word Select
0 = DMA transfers 1 byte per
request
1 = DMA transfers 2 bytes per
request
DMA0 Interrupt Enable
0 = DMA0 does not generate
interrupts
1 = DMA0 generates an interrupt
when
DMA0 Data Transfer Direction
0 = Register File to peripheral
registers
1 = Peripheral registers to Register
File
DMA0 Loop Enable
0 = DMA disables after End Address
1 = DMA reloads Start Address after
run
DMA0 Enable
0 = DMA0 is disabled
1 = DMA0 is enabled
DMA0 Peripheral Register Address
control
Low byte of on-chip peripheral
registers on Register File page FH
End Address data is transferred
End Address and continues to
contains valid data
contains valid data
DMA0 Address High Nibble
DMA0H (FB2H - Read/Write)
DMA0 Start/Current Address Low Byte
DMA0START (FB3H - Read/Write)
DMA0 End Address Low Byte
DMA0END (FB4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Z8 Encore! XP
DMA0 Start Address [11:8]
DMA0 End Address [11:8]
DMA0 Start Address [7:0]
DMA0 End Address [7:0]
Product Specification
Control Register Summary
®
F64XX Series
36