Z16F2810FI20EG Zilog, Z16F2810FI20EG Datasheet - Page 139

• Manufacturer Part Number: Z16F2810FI20EG
• Description: IC ZNEO MCU FLASH 128K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810FI20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-BQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 68. PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH, PWMLxDH)
Table 69. PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL, PWMLxDL)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
Bit Position
[7]
SIGN
[6:0], [7:0]
DUTYH
and
DUTYL
PWM Control 0 Register
SIGN
R/W
7
X
7
Writing a negative value (DUTYH[7] = 1) forces the PWM to be OFF for the full PWM
period. Writing a positive value greater than the 12-bit PWM reload value forces the PWM
to be ON for the full PWM period.
The PWM control 0 register (PWMCTL0) controls PWM operation.
Value (H) Description
0
1
FF_E390H, FF_E392H, FF_E394H, FF_E396H, FF_E398H, FF_E39AH
FF_E391H, FF_E393H, FF_E395H, FF_E397H, FF_E399H, FF_E39BH
PWM Duty Cycle
6
6
Duty cycle sign
Duty cycle is a positive two’s complement number.
Duty cycle is a negative two’s complement number.
Output is forced to the off-state.
PWM duty cycle high and low bytes
These two bytes, {DUTYH[7:0], DUTYL [7:0]}, form a 14 -bit signed value
(Bits 5 and 6 of the High byte are always 0). The value is compared to the
current 12-bit PWM count.
Reserved
R/W
XX
5
5
P R E L I M I N A R Y
=
100
4
4

DUTYL
PWM Duty Cycle Value
---------------------------------------------------------- -
XXH
R/W
PWM Reload Value
3
3
X_XXXX
DUTYH
R/W
2
2
Multi-Channel PWM Timer
Product Specification
ZNEO
1
1
Z16F Series
0
0
124