STM32F103VET6TR STMicroelectronics, STM32F103VET6TR Datasheet - Page 121

• Manufacturer Part Number: STM32F103VET6TR
• Description: MCU 32BIT ARM 512K FLASH 100-LQF
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F103VET6TR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 80
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: STM32F103x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: CAN, I2C, SPI, USART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 11
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: 497-10030 - STARTER KIT FOR STM32497-8511 - KIT STARTER FOR STM32 512K FLASH497-6438 - BOARD EVALUTION FOR STM32 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

STM32F103xC, STM32F103xD, STM32F103xE
Table 72.
30-Mar-2009
Date
Document revision history
Revision
5
I/O information clarified
STM32F103xE performance line BGA100 ballout
I/O information clarified
In
– I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15
– PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
PG14 pin description modified in
Figure 9: Memory map on page 38
Note modified in
code with data processing running from Flash
current consumption in Sleep mode, code running from Flash or
Figure
changed).
Table 21: High-speed external user clock characteristics
Low-speed external user clock characteristics
values modified in
FSMC configuration modified for
Notes modified below
SRAM/PSRAM/NOR read waveforms
non-multiplexed SRAM/PSRAM/NOR write
t
SRAM/PSRAM/NOR read timings
multiplexed PSRAM/NOR write
Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
timings
In
Table 38: Synchronous non-multiplexed PSRAM write
– t
– t
– t
Figure 28: Synchronous multiplexed NOR/PSRAM read
Figure 29: Synchronous multiplexed PSRAM write timings
Figure 31: Synchronous non-multiplexed PSRAM write timings
modified.
Figure 48: I2S slave timing diagram (Philips protocol)(1)
I2S master timing diagram (Philips protocol)(1)
WLCSP64 package added (see
STM32F103xE performance line WLCSP64 ballout, ball
High-density STM32F103xx pin
4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package
outline
pitch, wafer-level chip-scale package mechanical
Small text changes.
w(NADV)
updated
column to Remap column
Table 5: High-density STM32F103xx pin
Table 36: Synchronous multiplexed PSRAM write timings
v(Data-CLK)
d(CLKL-Data)
h(CLKL-DV)
Doc ID 14611 Rev 7
17,
and
values modified in
Figure 18
Table 66: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm
/ t
renamed as t
min value removed and max value added
h(CLKL-ADV)
Table 14: Maximum current consumption in Run mode,
Table 25: HSI oscillator
and
Figure 24: Asynchronous non-multiplexed
on page
on page
Figure 19
removed
d(CLKL-Data)
Table 31: Asynchronous non-multiplexed
Changes
timings. t
Figure 8: STM32F103xC and
definitions,
Asynchronous waveforms and
1.
Table 6: FSMC pin
1.
and
Figure 4: STM32F103xC and
modified.
show typical curves (titles
and
Table 34: Asynchronous
h(Data_NWE)
characteristics.
Figure 25: Asynchronous
definitions:
waveforms.
Figure 61: WLCSP, 64-ball
modified. ACC
and
modified.
data).
corrected.
Table 16: Maximum
definition.
Revision history
modified in
timings:
timings,
and
and
side,
and
and
Figure 49:
HSI
Table 22:
Table 5:
timings.
121/123
max
RAM.