STR911FAW47X6 STMicroelectronics, STR911FAW47X6 Datasheet - Page 32

• Manufacturer Part Number: STR911FAW47X6
• Description: MCU ARM9 2048KB FLASH 128LQFP
• Manufacturer: STMicroelectronics
• Series: STR9r

Specifications of STR911FAW47X6

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: STR911x
• Core: ARM966E-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 96 KB
• Interface Type: CAN, SPI, UART
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional overview
3.18.1
3.18.2
3.18.3
3.19
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Packet buffer interface (PBI)
The PBI manages a set of buffers inside the 2 Kbyte Packet Buffer, both for transmission
and reception. The PBI will choose the proper buffer according to requests coming from the
USB Serial Interface Engine (SIE) and locate it in the Packet SRAM according to addresses
pointed by endpoint registers. The PBI will also auto-increment the address after each
exchanged byte until the end of packet, keeping track of the number of exchanged bytes and
preventing buffer overrun. Special support is provided by the PBI for isochronous and bulk
transfers, implementing double-buffer usage which ensures there is always an available
buffer for a USB packet while the CPU uses a different buffer.
DMA
A programmable DMA channel may be assigned by CPU firmware to service the USB
interface for fast and direct transfers between the USB bus and SRAM with little CPU
involvement. This DMA channel includes the following features:
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Suspend mode
CPU firmware may place the USB interface in a low-power suspend mode when required,
and the USB interface will automatically wake up asynchronously upon detecting activity on
the USB pins.
CAN 2.0B interface
The STR91xFA provides a CAN interface complying with CAN protocol version 2.0 parts A
and B. An external CAN transceiver device connected to pins CAN_RX and CAN_TX is
required for connection to the physical CAN bus.
The CAN interface manages up to 32 Message Objects and Identifier Masks using a
Message SRAM and a Message Handler. The Message Handler takes care of low-level
CAN bus activity such as acceptance filtering, transfer of messages between the CAN bus
and the Message SRAM, handling of transmission requests, and interrupt generation. The
CPU has access to the Message SRAM via the Message Handler using a set of 38 control
registers.
The follow features are supported by the CAN interface:
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The CAN interface is not supported by DMA.
Direct USB Packet Buffer SRAM to system SRAM transfers of receive packets, by
descriptor chain for bulk or isochronous endpoints.
Direct system SRAM to USB Packet Buffer SRAM transfers of transmit packets, by
descriptor chain for bulk or isochronous endpoints.
Linked-list descriptor chain support for multiple USB packets
Bit rates up to 1 Mbps
Disable Automatic Retransmission mode for Time Triggered CAN applications
32 Message Objects
Each Message Object has its own Identifier Mask
Programmable FIFO mode
Programmable loopback mode for self-test operation
Doc ID 13495 Rev 6
STR91xFAxxx