MC9S08JM8CLC Freescale Semiconductor, MC9S08JM8CLC Datasheet - Page 51

• Manufacturer Part Number: MC9S08JM8CLC
• Description: MCU 8BIT 8K FLASH 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM8CLC

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 21
• Ram Memory Size: 1KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.5.5
An access error occurs when the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
Freescale Semiconductor
•
•
Writing to a flash address before the internal flash clock frequency has been set by writing to the
FCDIV register
Writing to a flash address while FCBEF is not set (a new command cannot be started until the
command buffer is empty)
1
2
PROGRAM FLOW
Required only once after reset.
Wait at least four bus cycles before checking FCBEF or FCCF.
FLASH BURST
Access Errors
Figure 4-3. Flash Burst Program Flowchart
YES
MC9S08JM16 Series Data Sheet, Rev. 2
WRITE COMMAND (0x25) TO FCMD
0
TO BUFFER ADDRESS AND DATA
NEW BURST COMMAND?
TO LAUNCH COMMAND
AND CLEAR FCBEF
WRITE 1 TO FCBEF
WRITE TO FCDIV
WRITE TO FLASH
CLEAR ERROR
FACCERR?
FACCERR?
FPVIO OR
FCBEF?
START
FCCF?
DONE
1
1
NO
1
NO
1
2
YES
0
0
ERROR EXIT
Chapter 4 Memory
51