MC9S08RD32DWE Freescale Semiconductor, MC9S08RD32DWE Datasheet - Page 135

• Manufacturer Part Number: MC9S08RD32DWE
• Description: IC MCU 32K FLASH 2K RAM 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32DWE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

register (TPM1CnVH:TPM1CnVL). The polarity of this PWM signal is determined by the setting in the
ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible.
As
(duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the
pulse width. If ELSnA = 0, the counter overflow forces the PWM signal high and the output compare
forces the PWM signal low. If ELSnA = 1, the counter overflow forces the PWM signal low and the output
compare forces the PWM signal high.
When the channel value register is set to $0000, the duty cycle is 0 percent. By setting the timer channel
value register (TPM1CnVH:TPM1CnVL) to a value greater than the modulus setting, 100 percent duty
cycle can be achieved. This implies that the modulus setting must be less than $FFFF to get 100 percent
duty cycle.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register,
TPM1CnVH or TPM1CnVL, write to buffer registers. In edge-PWM mode, values are transferred to the
corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and
the value in the TPM1CNTH:TPM1CNTL counter is $0000. (The new duty cycle does not take effect until
the next full period.)
10.5.3
This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The
output compare value in TPM1CnVH:TPM1CnVL determines the pulse width (duty cycle) of the PWM
signal and the period is determined by the value in TPM1MODH:TPM1MODL.
TPM1MODH:TPM1MODL should be kept in the range of $0001 to $7FFF because values outside this
range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output.
If the channel value register TPM1CnVH:TPM1CnVL is zero or negative (bit 15 set), the duty cycle will
be 0 percent. If TPM1CnVH:TPM1CnVL is a positive value (bit 15 clear) and is greater than the (nonzero)
modulus setting, the duty cycle will be 100 percent because the duty cycle compare will never occur. This
implies the usable range of periods set by the modulus register is $0001 through $7FFE ($7FFF if
Freescale Semiconductor
Figure 10-3
Center-Aligned PWM Mode
shows, the output compare value in the TPM channel registers determines the pulse width
TPM1C
OVERFLOW
Figure 10-3. PWM Period and Pulse Width (ELSnA = 0)
pulse width = 2 x (TPM1CnVH:TPM1CnVL)
PULSE
WIDTH
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
period = 2 x (TPM1MODH:TPM1MODL);
PERIOD
COMPARE
for TPM1MODH:TPM1MODL = $0001–$7FFF
OUTPUT
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
Timer/PWM (TPM)
Eqn. 10-1
Eqn. 10-2
135