MC9S08RD32DWE Freescale Semiconductor, MC9S08RD32DWE Datasheet - Page 169

• Manufacturer Part Number: MC9S08RD32DWE
• Description: IC MCU 32K FLASH 2K RAM 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32DWE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When CPHA = 1, the slave begins to drive its MISO output when SS1 goes to active low, but the data is
not defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter
onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both
the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the
third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,
and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the
master and slave, respectively. When CHPA = 1, the slave’s SS input is not required to go to its inactive
high level between transfers.
Figure 13-6
for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK
edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting in LSBFE.
Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific
transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a
slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master
and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the
slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active
low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after the end
of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave.
Freescale Semiconductor
(MISO OR MOSI)
(MASTER OUT)
(REFERENCE)
(SLAVE OUT)
SAMPLE IN
MSB FIRST
BIT TIME #
(CPOL = 0)
(CPOL = 1)
LSB FIRST
(MASTER)
(SLAVE)
SS OUT
SPSCK
SPSCK
SS IN
MOSI
MISO
shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are shown
BIT 7
BIT 0
1
Figure 13-6. SPI Clock Formats (CPHA = 0)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
BIT 6
BIT 1
2
...
...
...
BIT 2
BIT 5
6
BIT 1
BIT 6
7
Serial Peripheral Interface (SPI) Module
BIT 0
BIT 7
8
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