MCHC908GR8AMFAE Freescale Semiconductor, MCHC908GR8AMFAE Datasheet - Page 38

• Manufacturer Part Number: MCHC908GR8AMFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AMFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory
2.5 Random-Access Memory (RAM)
Addresses $0040 through $01BF are RAM locations. The location of the stack RAM is programmable.
The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
Within page zero are 192 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently
access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU
registers.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
2.6 FLASH Memory (FLASH)
This subsection describes the operation of the embedded FLASH memory. This memory can be read,
programmed, and erased from a single external supply. The program, erase, and read operations are
enabled through the use of an internal charge pump.
2.6.1 Functional Description
The FLASH memory is an array of 7,680 bytes for the MC68HC908GR8A or 4,096 bytes for the
MC68HC908GR4A with an additional 36 bytes of user vectors and one byte of block protection. An
erased bit reads as 1 and a programmed bit reads as a 0. Memory in the FLASH array is organized into
two rows per page basis. The page size is 64 bytes per page and the row size is 32 bytes per row. Hence
the minimum erase page size is 64 bytes and the minimum program row size is 32 bytes. Program and
erase operation operations are facilitated through control bits in FLASH control register (FLCR). Details
for these operations appear later in this section.
The address ranges for the user memory and vectors are:
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
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unauthorized users.
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$E000–$FDFF; user memory for the MC68HC908GR8A
$EE00–$FDFF; user memory for the MC68HC908GR4A
$FE08
$FF7E; FLASH block protect register
$FFDC–$FFFF; these locations are reserved for user-defined interrupt and reset vectors
;
FLASH control register
For correct operation, the stack pointer must point only to RAM locations.
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
A security feature prevents viewing of the FLASH contents.
For M6805 compatibility, the H register is not stacked.
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
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Freescale Semiconductor