R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 135

• Manufacturer Part Number: R5F2121AJFP#U0
• Description: MCU FLASH 96K 5K CMOS 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/21r

Specifications of R5F2121AJFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
13.2
Table 13.3
NOTES:
Count Source
Count Operation
Period
Count Start Condition
Reset Condition of Watchdog
Timer
Count Stop Condition
Operation at the Time of
Underflow
Register, Bit
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when the program is out of control, the clock can be supplied to the
watchdog timer.
Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled).
1. The WDTON bit cannot be changed by a program. When setting the WDTON bit, write 0 to the bit 0
2. Even if writing 0 to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI
of the address 0FFFFh using a flash programmer.
bit cannot be changed by a program. When setting the CSPROINI bit, write 0 to the bit 7 of the
address 0FFFFh using a flash programmer.
Count Source Protection Mode Enabled
Watchdog Timer Specifications (with Count Source Protection Mode Enabled)
Item
Page 117 of 458
Low-speed on-chip oscillator clock
Decrement
Count value of watchdog timer (4096)
e.g. Period is approximately 32.8 ms when the low-speed on-chip
The WDTON bit
of the watchdog timer after reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state
• When the WDTON bit is set to 0 (watchdog timer starts
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
None (the count does not stop in wait mode after the count starts. The
MCU does not enter stop mode)
Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)
• When setting the CSPPRO bit in the CSPR register to 1 (count
• The following states are held in count source protection mode
Low-speed on-chip oscillator clock
automatically after reset)
The watchdog timer and prescaler start counting automatically after
reset
after reset)
starts by writing to the WDTS register
source protection mode is enabled)
automatically
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is
The watchdog timer and prescaler stop after reset and the count
- Writing to the CM14 bit in the CM1 register disables (It remains
- Writing to the CM10 bit in the CM1 register disables (It remains
unchanged even if it is set to 1. The MCU does not enter stop
mode)
unchanged even if it is set to 1. The low-speed on-chip oscillator
does not stop)
oscillator on)
reset when watchdog timer underflows)
oscillator clock is 125 kHz
(1)
in the OFS register (0FFFFh) selects the operation
Specification
(2)
, the following are set
13. Watchdog Timer