R5F2121AJFP#U0 Renesas Electronics America, R5F2121AJFP#U0 Datasheet - Page 253

MCU FLASH 96K 5K CMOS 48-LQFP

R5F2121AJFP#U0

Manufacturer Part Number
R5F2121AJFP#U0
Description
MCU FLASH 96K 5K CMOS 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/21r
Datasheet

Specifications of R5F2121AJFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F2121AJFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R5F2121AJFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
Figure 14.97
TSTART0 and TSTART1
bits in TRDSTR register
TRDGRD0 register
TRDGRB0 register
TRDSR1 register
TRDSR0 register
TRDSR0 register
TRDIOB0 output
TRDIOD0 output
TRDIOC0 output
IMFA bit in
IMFB bit in
UDF bit in
Count source
Value in TRDi register
0000h
m + 1
Operating Example of Complementary PWM Mode
CMD0, CMD1: Bits in TRDFCR register
i = 0 or 1
The above applies to the following conditions:
The OLS1 and OLS0 bits in the TRDFCR are set to 0 (initial output level “H”, active level “L” for normal-phase and counter-phase)
1
0
1
0
1
0
1
0
m
n
p
Initial output “H”
Initial output “H”
Page 235 of 458
Transfer (When the CMD1 to CMD0 bits are set to 11b)
Active level “L”
n + 1 - p
n + 1
m + 2 - p
n
n
p
m - p - n + 1
phase active level
(m - p - n + 1) × 2
Width of normal-
Set to 0 by a program
Set to 0 by a program
Dead
time
p
m: Setting Value in TRDGRA0 register
n: Setting Value in TRDGRB0 register
p: Setting Value in TRD0 register
Width of counter-phase active level
Transfer (When the CMD1 to CMD0 bits
Value in TRD0 register
are set to 10b)
n
Value in TRD1 register
Modify with a program
(n + 1 - p) × 2
n + 1 - p
Following data
Set to 0 by a program
FFFFh
Set to
14. Timers

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