M38504E6FP#U0 Renesas Electronics America, M38504E6FP#U0 Datasheet
M38504E6FP#U0
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M38504E6FP#U0 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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Group (Spec.H/A) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 3850 Group (Spec.H) DESCRIPTION The 3850 group (spec the 8-bit microcomputer based on the 740 family core technology. The 3850 group (spec designed for the household products and office ...
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Group (Spec.A) DESCRIPTION The 3850 group (spec the 8-bit microcomputer based on the 740 family core technology. The 3850 group (spec designed for the household products and office automation equipment and includes serial I/O functions, ...
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Group (Spec.H) FUNCTIONAL BLOCK Fig. 3 Functional block diagram (spec. H) Rev.3.01 2003.06.20 page ...
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Group (Spec.A) Fig. 4 Functional block diagram (spec. A) Rev.3.01 2003.06.20 page ...
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Group (Spec.H) Table 1 Pin description (spec. H) Pin Name Power source CNV CNV input SS SS Reset input RESET X Clock input IN X Clock output OUT IN2 P0 /S ...
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Group (Spec.A) Table 2 Pin description (spec. A) Pin Name Power source CC SS CNV CNV input SS SS Reset input RESET X Clock input IN X Clock output OUT IN2 P0 /S ...
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Group (Spec.H/A) PART NUMBERING Product name M3850 Fig. 5 Part numbering Rev.3.01 2003.06.20 page A– XXX SP Package type SP : 42P4B FP : 42P2R-A 42S1B-A ROM number Omitted in One ...
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Group (Spec.H/A) GROUP EXPANSION Renesas Technology plans to expand the 3850 group (spec. H/A) as follows. Memory Type Support for mask ROM, One Time PROM, and flash memory ver- sions. Memory Size Flash memory size ......................................................... 32 K bytes ...
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Group (Spec.H/A) Currently planning products are listed below. Table 3 Support products (spec. H) ROM size (bytes) Product name ROM size for User in ( M38503M2H-XXXSP 8192 (8062) M38503M2H-XXXFP M38503M4H-XXXSP 16384 (16254) M38503M4H-XXXFP M38504M6-XXXSP M38504E6-XXXSP M38504E6SP 24576 M38504E6SS (24446) ...
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Group (Spec.H/A) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3850 group (spec. H/A) uses the standard 740 Family instruc- tion set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual ...
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Group (Spec.H/A) Interrupt request ...
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Group (Spec.H/A) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions ...
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Group (Spec.H/A) [CPU Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B b 7 Fig. 9 Structure of CPU mode register Rev.3.01 2003.06.20 page ...
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Group (Spec.H/A) MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine ...
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Group (Spec. ...
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Group (Spec.A) Port P0 (P0) 0000 16 Port P0 direction register (P0D) 0001 16 Port P1 (P1) 0002 16 Port P1 direction register (P1D) 0003 16 Port P2 (P2) 0004 16 Port P2 direction register (P2D) 0005 16 Port ...
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Group (Spec.H) I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input ...
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Group (Spec.A) I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input ...
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Group (Spec.H) (1) Port P0 0 Direction register Port latch Data bus Serial I/O2 input (3) Port P-channel output disable bit 2 CLK2 Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction ...
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Group (Spec.H) (9) Port P2 4 Serial I/O1 enable bit Receive enable bit Direction register Port latch Data bus Serial I/O1 input (11) Port P2 6 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode ...
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Group (Spec.H) Fig. 15 Port block diagram (3) (spec. H) Rev.3.01 2003.06.20 page (17) Port P4 4 PWM output enable bit Direction register Port latch Data bus PWM output Interrupt input ...
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Group (Spec.A) (1) Port P0 0 Pull-up control bit Direction register Port latch Data bus Serial I/O2 input (3) Port P0 2 Pull-up control bit P0 /S P-channel output disable bit 2 CLK2 Serial I/O2 synchronous clock selection bit ...
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Group (Spec.A) (9) Port ...
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Group (Spec.A) Fig. 18 Port block diagram (3) (spec. A) Rev.3.01 2003.06.20 page Pull-up control bit ...
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Group (Spec. Fig. 19 Structure of port registers (1) (spec. A) Rev.3.01 2003.06.20 page Port P0, P1, P2 pull-up control register (PULL012: address 0012 ) 16 P0 pull-up control bit 0: No ...
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Group (Spec. Fig. 20 Structure of port registers (2) (spec. A) Rev.3.01 2003.06.20 page Port P4 pull-up control register (PULL4: address 0014 ) 16 P4 pull-up control bit pull-up ...
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Group (Spec.H/A) INTERRUPTS Interrupts occur by 15 sources among 15 sources: six external, eight internal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except ...
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Group (Spec.H/A) Table 10 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High 1 FFFD Reset (Note 2) INT 0 2 FFFB Reserved 3 FFF9 INT 1 4 FFF7 INT 5 FFF5 2 INT / ...
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Group (Spec.H/A) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Fig. 21 Interrupt control ...
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Group (Spec.H/A) TIMERS The 3850 group (spec. H/A) has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value ...
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Group (Spec.H/ ...
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Group (Spec.H/A) SERIAL I/O SERIAL I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation ...
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Group (Spec.H/A) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats ...
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Group (Spec.H/A) Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output Receive buffer read signal ST Serial input Notes 1: Error flag detection occurs at the same time ...
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Group (Spec.H/ ...
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Group (Spec.H/A) SERIAL I/O2 The serial I/O2 can be operated only as the clock synchronous type synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection ...
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Group (Spec.H/ ...
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Group (Spec.H/A) S CMP2 S CLK2 S OUT2 S IN2 Fig output operation CMP2 Rev.3.01 2003.06.20 page Judgement of I/O data comparison ...
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Group (Spec.H/A) PULSE WIDTH MODULATION (PWM) The 3850 group (spec. H/A) has a PWM function with an 8-bit resolution, based on a signal that is the clock input X clock input divided by 2. Data Setting The PWM output ...
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Group (Spec.H/ ...
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Group (Spec.H) A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 0035 , 0036 16 16 The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion. [A-D ...
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Group (Spec.A) A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 0035 , 0036 16 16 The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion. [A-D ...
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Group (Spec. ...
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Group (Spec.H/A) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an ...
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Group (Spec.H/A) RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an “L” level for 20 cycles or more Then the RESET pin is returned “H” level (the power source ...
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Group (Spec.H) (1) Port P0 (P0) (2) Port P0 direction register (P0D) (3) Port P1 (P1) (4) Port P1 direction register (P1D) (5) Port P2 (P2) (6) Port P2 direction register (P2D) (7) Port P3 (P3) (8) Port P3 ...
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Group (Spec. ...
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Group (Spec.H/A) CLOCK GENERATING CIRCUIT The 3850 group (spec. H/A) has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator be- tween X and X (X and X IN OUT CIN COUT in accordance ...
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Group (Spec.H/A) [MISRG (MISRG)] 0038 16 MISRG consists of three control bits (bits for middle-speed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after STP instruction released. By setting the ...
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Group (Spec.H/A) Reset Middle-speed mode CM ( MHz) “1” MHz oscillating (32 kHz stopped) 4 Middle-speed mode CM (f( ) ...
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Group (Spec.H/A) FLASH MEMORY MODE The M38507F8 (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when V CC when and ...
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Group (Spec.H/A) (1) CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Process- ing Unit (CPU). In CPU rewrite mode, only the User ROM ...
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Group (Spec.H/A) Outline Performance (CPU Rewrite Mode) CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten in CPU rewrite mode. In CPU rewrite mode, the CPU erases, programs and ...
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Group (Spec.H/A) Notes 1: When starting the MCU in the single-chip mode, supply 4 5. the CNVss pin until checking the CPU rewrite mode entry flag. 2: Set bits 6, 7 (main clock division ratio ...
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Group (Spec.H/A) Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the internal clock frequency 6.25 MHz or ...
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Group (Spec.H/A) Software Commands (CPU Rewrite Mode) Table 12 lists the software commands. After setting the CPU Rewrite Mode Select Bit of the flash memory control register to “1”, execute a software command to specify an erase or program ...
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Group (Spec.H/A) Erase All Blocks Command (20 / writing the command code “20 ” in the first bus cycle and the 16 confirmation command code “20 ” in the second bus cycle that 16 follows, the operation ...
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Group (Spec.H/A) Status Register (SRD) The status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. It can be read in the following ways: (1) By reading ...
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Group (Spec.H/A) Full Status Check By performing full status check possible to know the execu- tion results of erase and program operations. Figure 62 shows a Read status register YES SR4 = 1 and SR5 = 1 ...
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Group (Spec.H/A) Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and ...
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Group (Spec.H/A) ID Code Check Function (in Standard serial I/O mode) Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the pro- grammer is compared ...
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Group (Spec.H/A) (2) Parallel I/O Mode Parallel I/O mode is the mode which parallel output and input soft- ware command, address, and data required for the operations (read, program, erase, etc built-in flash memory. Use the ex- ...
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Group (Spec.H/A) (3) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. ...
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Group (Spec.H/A) Table 14 Description of pin function (Standard Serial I/O Mode) Pin Name V ,V Power input CC SS CNV CNV SS SS Reset input RESET X Clock input IN X Clock output OUT AV Analog power supply ...
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Group (Spec.H/A) P4 /INT 4 P4 /INT USY P2 /CNTR 7 S CLK1 P2 TxD R D RxD RESET 1 Signal Value 4 ...
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Group (Spec.H/A) Software Commands (Standard Serial I/O Mode) Table 15 lists software commands. In standard serial I/O mode, erase, program and read are controlled by transferring software Table 15 Software commands (Standard serial I/O mode) Control command 1 Page ...
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Group (Spec.H/A) Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. S CLK1 RxD TxD S (BUSY) RDY1 ...
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Group (Spec.H/A) Clear Status Register Command This command clears the bits (SR4, SR5) which are set when the status register operation ends in error. When the “50 code is sent with the 1st byte, the aforementioned bits are cleared. ...
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Group (Spec.H/A) Erase All Blocks Command This command erases the contents of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the “A7 ” command code with the 1st byte. 16 (2) Transfer the ...
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Group (Spec.H/A) Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA ” command code with the 1st byte. 16 (2) Transfer the program size ...
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Group (Spec.H/A) Version Information Output Command This command outputs the version information of the control pro- gram stored in the Boot ROM area. Execute the version information output command as explained here following. S CLK1 RxD TxD S (BUSY) ...
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Group (Spec.H/A) ID Check This command checks the ID code. Execute the boot ID check command as explained here following. S CLK1 F5 RxD TxD S (BUSY) RDY1 Fig. 73 Timing for ID check ID Code When the flash ...
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Group (Spec.H/A) Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read ...
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Group (Spec.H/A) Status Register 1 (SRD1) The status register 1 indicates the status of serial communica- tions, results from ID checks and results from check sum comparisons. It can be read after the status register (SRD) by writ- ing ...
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Group (Spec.H/A) Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 75 shows a flowchart of the full status check and explains how to remedy errors which occur. ...
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Group (Spec.H/A) Example Circuit Application for Standard Serial I/O Mode Figure 76 shows a circuit application for the standard serial I/O mode. Control pins will vary according to a programmer, therefore see a programmer manual for more information. Clock ...
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Group (Spec.H/A) Flash memory Electrical characteristics Table 18 Absolute maximum ratings Symbol Parameter V Power source voltage CC Input voltage P0 – – REF V Input voltage ...
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Group (Spec.H/A) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect ...
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Group (Spec.H/A) Electric Characteristic Differences Among Mask ROM, Flash Memory, and One Time PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM, flash memory, and One Time PROM version ...
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Group (Spec.H/A) Electrical characteristics Absolute maximum ratings Table 21 Absolute maximum ratings Symbol Parameter V Power source voltage CC Input voltage P0 – – REF Input voltage ...
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Group (Spec.H) Recommended operating conditions Table 22 Recommended operating conditions (1) (spec 2 – unless otherwise noted Symbol Power source voltage Power source ...
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Group (Spec.A) Recommended operating conditions Table 23 Recommended operating conditions (1) (spec 2 – unless otherwise noted Symbol V Power source voltage CC V Power source ...
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Group (Spec.H) Table 24 Recommended operating conditions (2) (spec 2 – unless otherwise noted) CC Symbol I “H” peak output current OH(peak) I “L” peak output current (Note ...
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Group (Spec.A) Table 26 Recommended operating conditions (2) (spec 2 – unless otherwise noted) CC Symbol I “H” peak output current OH(peak) I “L” peak output current (Note ...
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Group (Spec.H) Table 28 Electrical characteristics (2) (spec. 2 – unless otherwise noted Symbol Parameter V –V Hysteresis T+ T– CNTR , ...
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Group (Spec.A) Table 29 Electrical characteristics (2) (spec. 2 – unless otherwise noted Symbol Parameter V –V Hysteresis T+ T– CNTR , ...
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Group (Spec.H) Table 30 Electrical characteristics (3) (spec 2 – unless otherwise noted Symbol Parameter I High-speed mode Power source current ...
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Group (Spec.A) Table 31 Electrical characteristics (3) (spec 2 – unless otherwise noted Symbol Parameter I High-speed mode Power source current ...
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Group (Spec.H) A-D converter characteristics Table 32 A-D converter characteristics (spec 2 Symbol Parameter – Resolution – Absolute accuracy (excluding quantization error) t ...
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Group (Spec.A) A-D converter characteristics Table 33 A-D converter characteristics (spec 2 Symbol Parameter – Resolution – Absolute accuracy (excluding quantization error) t ...
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Group (Spec.H) Timing requirements Table 34 Timing requirements (1) (spec 4 – unless otherwise noted Symbol Reset input “L” pulse width ...
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Group (Spec.A) Timing requirements Table 36 Timing requirements (1) (spec 4 – unless otherwise noted Symbol Reset input “L” pulse width ...
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Group (Spec.H/A) Switching characteristics Table 38 Switching characteristics ( 4 – unless otherwise noted Symbol Serial I/O1 clock output ...
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Group (Spec.H/ Fig. 78 Circuit for measuring output switching characteristics Rev.3.01 2003.06.20 page ...
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Group (Spec.H/A) CNTR 0 CNTR ...
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Group (Spec.H/A) PACKAGE OUTLINE 42P4B MMP EIAJ Package Code JEDEC Code SDIP42-P-600-1.78 – SEATING PLANE 42P2R-A/E EIAJ Package Code JEDEC Code SSOP42-P-450-0.80 – Detail G 1 Rev.3.01 2003.06.20 page 96 of ...
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Group (Spec.H/A) 42S1B-A EIAJ Package Code JEDEC Code WDIP42-C-600-1. Rev.3.01 2003.06.20 page Weight(g) – SEATING PLANE Metal seal 42pin 600mil DIP 22 21 Dimension in Millimeters Symbol Min ...
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Group (Spec.H/A) Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with ...
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REVISION HISTORY Rev. Date 1.0 03/09/00 Page 1.00 – First edition issued Mar. 9, 2000 1.10 Font errors are revised. Mar. 22, 2000 2.00 1 Dec. 22, 2000 “lnterrupts” of “FEATURES” is revised. 1 Figure 1 is partly revised. 6 ...
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REVISION HISTORY Rev. Date Page 3.00 57 Explanations of “ Erase All Blocks Command (20 May. 29, 2002 57 Explanations of “ Block Erase Command (20 58 Explanations of “Status Register (SRD)” are partly revised. 59 Figure 62 is partly ...
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REVISION HISTORY Rev. Date Page 3.01 88 Limit of the high-speed mode [f(X Jun. 20, 2003 Limit of the high-speed mode [f(X Limit of the middle-speed mode [f(X 3850 Group (Spec.H/A) Data Sheet Description Typ. : 7.5 mA 6.5 mA, ...