R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 373

• Manufacturer Part Number: R4F24268NVRFQV
• Description: MCU 256KB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVRFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt
request, and reactivating channel 0A. The address register and count register areas are set again
during the first DTC transfer, then the control register area is set again during the second DTC
chain transfer. When re-setting the control register area, perform masking by setting bits in
DMAWER to prevent modification of the contents of other channels.
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)
DTC
First transfer area
Second transfer area
using chain transfer
DMACR_0A
DMACR_1A
DMAWER
MAR_0AH
MAR_0BH
MAR_1AH
MAR_1BH
MAR_0AL
ETCR_0A
MAR_0BL
ETCR_0B
MAR_1AL
ETCR_1A
MAR_1BL
ETCR_1B
IOAR_0A
IOAR_0B
IOAR_1A
IOAR_1B
DMABCR
Section 7 DMA Controller (DMAC)
DMACR_0B
DMACR_1B
DMATCR
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