R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 380

• Manufacturer Part Number: R4F24268NVRFQV
• Description: MCU 256KB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVRFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
7.5.2
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.5 summarizes register functions in sequential mode.
Table 7.5
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Page 350 of 1372
Register
23
23
H'FF
15
Sequential Mode
15
Register Functions in Sequential Mode
ETCR
MAR
IOAR
0
0
0
DTDIR = 0 DTDIR = 1 Initial Setting
Source
address
register
Destination
address
register
Transfer counter
Function
Destination
address
register
Source
address
register
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Operation
Incremented/
decremented every
transfer
Fixed
transfer; transfer
ends when count
reaches H'0000
Jul 09, 2010