R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 990

• Manufacturer Part Number: R4F24268NVRFQV
• Description: MCU 256KB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVRFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I2C Bus Interface 2 (IIC2)
16.3.1
ICCRA is an 8-bit readable/writable register that enables or disables the I
transmission or reception, and selects master or slave mode, transmission or reception, and
transfer clock frequency in master mode.
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Bit
7
6
5
4
3
2
1
0
Bit Name
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0
I
2
C Bus Control Register A (ICCRA)
0
0
0
0
0
0
0
0
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
I
0: Disables SCL/SDA outputs. (Inputs to SCL/SDA
1: This module is enabled for transfer operations.
Reception Disable
This bit enables or disables the next operation
when TRS is 0 and ICDRR is read.
0: Enables next reception.
1: Disables next reception.
Master/Slave Select
Transmit/Receive Select
When arbitration is lost in master mode, MST and
TRS are both reset by hardware, causing a
transition to slave receive mode. Modification of
the TRS bit should be made between transfer
frames. In addition, TRS is set to 1 automatically
in slave receive mode if the seventh bit of the start
condition matches the slave address set in SAR
and the eighth bit is set to 1.
Operating modes are described below according
to MST and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Transfer Clock Select 3 to 0
In the master mode, these bits should be set
according to the necessary transfer rate (see table
16.2). In the slave mode, they are used to secure
the data setup time in transmit mode. The data
setup time is 10 tcyc if CKS3 is cleared to 0 and
20 tcyc if CKS3 is set to 1.
2
C Bus Interface Enable
are available.)
(SCL and SDA pins are bus drive state.)
H8S/2426, H8S/2426R, H8S/2424 Group
2
C bus interface, controls
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010