DF2378RVFQ34V Renesas Electronics America, DF2378RVFQ34V Datasheet - Page 881

• Manufacturer Part Number: DF2378RVFQ34V
• Description: IC H8S MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the
17.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when A/D conversion start delay time (t
conversion. Figure 17.2 shows the A/D conversion timing. Table 17.3 indicates the A/D
conversion time.
As indicated in figure 17.2, the A/D conversion time (t
time (t
total conversion time therefore varies within the ranges indicated in tables 17.3.
In scan mode, the values given in tables 17.3 apply to the first conversion time. The values given
in tables 17.4 apply to the second and subsequent conversions.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first
channel in the group starts again.
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel in the group.
SPL
). The length of t
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCSR. The
D
) passes after the ADST bit is set to 1, then starts
CONV
Rev.7.00 Mar. 18, 2009 page 813 of 1136
) includes t
D
Section 17 A/D Converter
and the input sampling
REJ09B0109-0700