HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 16

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Section 5 Interrupt Controller (INTC)
5.1
5.2
Rev. 7.00 Jan 31, 2006 page xiv of xxvi
Overview........................................................................................................................... 51
4.1.1
4.1.2
4.1.3
Resets ................................................................................................................................ 56
4.2.1
4.2.2
4.2.3
Address Errors .................................................................................................................. 58
4.3.1
4.3.2
Interrupts ........................................................................................................................... 59
4.4.1
4.4.2
4.4.3
Instruction Exceptions....................................................................................................... 61
4.5.1
4.5.2
4.5.3
4.5.4
Cases in which Exceptions are Not Accepted ................................................................... 63
4.6.1
4.6.2
Stack Status after Exception Handling.............................................................................. 64
Notes ................................................................................................................................. 65
4.8.1
4.8.2
4.8.3
Overview........................................................................................................................... 67
5.1.1
5.1.2
5.1.3
5.1.4
Interrupt Sources ............................................................................................................... 70
5.2.1
5.2.2
5.2.3
Exception Handling Types and Priorities ............................................................ 51
Exception Handling Operation............................................................................. 53
Exception Vector Table ....................................................................................... 54
Reset Types.......................................................................................................... 56
Power-On Reset ................................................................................................... 57
Manual Reset ....................................................................................................... 57
Address Error Sources ......................................................................................... 58
Address Error Exception Handling ...................................................................... 58
Interrupt Sources.................................................................................................. 59
Interrupt Priority Rankings .................................................................................. 59
Interrupt Exception Handling............................................................................... 60
Types of Instruction Exceptions .......................................................................... 61
Trap Instruction.................................................................................................... 61
Illegal Slot Instruction.......................................................................................... 62
General Illegal Instructions.................................................................................. 62
Immediately after Delayed Branch Instruction .................................................... 63
Immediately after Interrupt-Disabling Instruction ............................................... 63
Value of the Stack Pointer (SP) ........................................................................... 65
Value of the Vector Base Register (VBR) ........................................................... 65
Address Errors Caused by Stacking During Address Error Exception Handling
Features................................................................................................................ 67
Block Diagram..................................................................................................... 67
Pin Configuration................................................................................................. 69
Registers............................................................................................................... 69
NMI Interrupts ..................................................................................................... 70
User Break Interrupt ............................................................................................ 70
IRQ Interrupts ...................................................................................................... 70
......................................................................................... 51
........................................................................... 67
65