HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 205

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2. Bus release procedure
c. Refresh cycle + bus cycle
The bus release procedure is shown in figure 8.47. Figure 8.47 shows the case where BREQ is
input one state before the break between bus cycles so that tBRQS is satisfied. In the SH7032
and SH7034, the bus is released after the bus cycle in which BREQ is input (if BREQ is input
between bus cycles, after the bus cycle starting next).
The bus is never released during a refresh cycle and the following bus cycle ((a) or (b)
above)) (figure 8.46).
RAS, CAS
A21 to A0
RD, WR
BREQ
BACK
CSn
CK
Figure 8.46 Refresh Cycle and Following Bus Cycle
t
BRQS
Bus cycle
The bus is released after the bus
cycle in which BREQ is input
(if BREQ is input between bus cycles,
after the bus cycle starting next).
Figure 8.47 Bus Release Procedure
Refresh cycle
Cycle during which bus
is not released
high-level output
Strobe pin:
t
t
BZD
BZD
1 bus cycle
t
BACD1
Rev. 7.00 Jan 31, 2006 page 177 of 658
high impedance
Address & data
strobe pins:
Section 8 Bus State Controller (BSC)
t
Bus release
BRQS
t
BACD2
Bus cycle restart
Bus cycle
REJ09B0272-0700