HD6473834HV Renesas Electronics America, HD6473834HV Datasheet
HD6473834HV
Specifications of HD6473834HV
Available stocks
Related parts for HD6473834HV
HD6473834HV Summary of contents
Page 1
To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
Page 2
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
Page 3
To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
Page 4
Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
Page 5
H8/3834 Series 8 Hardware Manual H8/3837 H8/3836 H8/3835 H8/3834 H8/3833 H8/3832 HD6433837, HD6433837S, HD64473837 HD6433836, HD6433836S HD6433835, HD6433835S HD6433834, HD6433834S, HD6473834 HD6433833, HD6433833S HD6433832S Rev.5.0 2003.05 ...
Page 6
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole ...
Page 7
The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3834 Series has a system-on-a-chip architecture that includes ...
Page 8
...
Page 9
Section 1 Overview ............................................................................................................ 1.1 Overview ............................................................................................................................ 1.2 Internal Block Diagram ...................................................................................................... 1.3 Pin Arrangement and Functions ......................................................................................... 1.3.1 Pin Arrangement ................................................................................................... 1.3.2 Pin Functions......................................................................................................... Section 2 CPU ...................................................................................................................... 13 2.1 Overview ............................................................................................................................ 13 2.1.1 Features ................................................................................................................. 13 2.1.2 Address ...
Page 10
Memory Map...................................................................................................................... 46 2.8.1 Memory Map......................................................................................................... 46 2.8.2 LCD RAM Address Relocation ............................................................................ 52 2.9 Application Notes............................................................................................................... 53 2.9.1 Notes on Data Access............................................................................................ 53 2.9.2 Notes on Bit Manipulation .................................................................................... 55 2.9.3 Notes on Use of the EEPMOV Instruction ...
Page 11
Oscillator Settling Time after Standby Mode is Cleared ...................................... 100 5.3.4 Transition to Standby Mode and Port Pin States .................................................. 101 5.4 Watch Mode ....................................................................................................................... 101 5.4.1 Transition to Watch Mode .................................................................................... 101 5.4.2 Clearing Watch Mode ........................................................................................... 102 ...
Page 12
Overview ............................................................................................................................ 131 8.2 Port 1 .................................................................................................................................. 133 8.2.1 Overview ............................................................................................................... 133 8.2.2 Register Configuration and Description................................................................ 133 8.2.3 Pin Functions......................................................................................................... 137 8.2.4 Pin States ............................................................................................................... 139 8.3 Port 2 .................................................................................................................................. 140 8.3.1 Overview ............................................................................................................... 140 8.3.2 Register Configuration ...
Page 13
Pin States ............................................................................................................... 167 8.10 Port 9 .................................................................................................................................. 168 8.10.1 Overview ............................................................................................................... 168 8.10.2 Register Configuration and Description................................................................ 168 8.10.3 Pin Functions......................................................................................................... 169 8.10.4 Pin States ............................................................................................................... 171 8.11 Port A.................................................................................................................................. 171 8.11.1 Overview ............................................................................................................... 171 8.11.2 Register Configuration ...
Page 14
Register Descriptions ............................................................................................ 212 9.6.3 Noise Canceller Circuit ......................................................................................... 215 9.6.4 Timer Operation .................................................................................................... 217 9.6.5 Application Notes.................................................................................................. 221 9.6.6 Sample Timer G Application ................................................................................ 224 Section 10 Serial Communication Interface 10.1 Overview ........................................................................................................................... 225 10.2 SCI1.................................................................................................................................... 225 10.2.1 ...
Page 15
Features ................................................................................................................. 301 12.1.2 Block Diagram ...................................................................................................... 301 12.1.3 Pin Configuration .................................................................................................. 302 12.1.4 Register Configuration.......................................................................................... 302 12.2 Register Descriptions.......................................................................................................... 303 12.2.1 A/D Result Register (ADRR)................................................................................ 303 12.2.2 A/D Mode Register (AMR) .................................................................................. 303 12.2.3 A/D Start Register (ADSR)................................................................................... ...
Page 16
Power Supply Voltage and Operating Range........................................................ 345 14.3.2 DC Characteristics ................................................................................................ 347 14.3.3 AC Characteristics ................................................................................................ 352 14.3.4 A/D Converter Characteristics .............................................................................. 356 14.3.5 LCD Characteristics .............................................................................................. 357 14.4 H8/3832S, H8/3833S, H8/3834S, H8/3835S, H8/3836S and H8/3837S Absolute Maximum Ratings ...
Page 17
A/D Converter Characteristics .............................................................................. 426 14.11.5 LCD Characteristics .............................................................................................. 427 14.12 H8/3835, H8/3836, and H8/3837 Electrical Characteristics (Wide Temperature Range (I-Spec) Version) .................................................................... 429 14.12.1 Power Supply Voltage and Operating Range........................................................ 429 14.12.2 DC Characteristics ................................................................................................ 431 14.12.3 AC ...
Page 18
Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3834 Series features an on-chip liquid crystal display ...
Page 19
Table 1.1 Features (cont) Item Description CPU Typical instructions Multiply (8 bits 8 bits) Divide (16 bits Bit accumulator Register-indirect designation of bit position Interrupts 33 interrupt sources 13 external interrupt pins: IRQ 20 internal interrupt sources Clock pulse generators ...
Page 20
Table 1.1 Features (cont) Item Description Timer B: 8-bit timer Timers Timer C: 8-bit timer Timer F: 16-bit timer Timer G: 8-bit timer Serial communication Three channels on chip interface SCI1: synchronous serial interface Choice of 8-bit or 16-bit data ...
Page 21
Table 1.1 Features (cont) Item Description Product lineup Mask ROM Version HD6433832SH HD6433832SF HD6433832SX HD6433833H HD6433833SH HD6433833F HD6433833SF HD6433833X HD6433833SX HD6433834H HD6433834SH HD6433834F HD6433834SF HD6433834X HD6433834SX HD6433835H HD6433835SH HD6433835F HD6433835SF HD6433835X HD6433835SX HD6433836H HD6433836SH HD6433836F HD6433836SF HD6433836X HD6433836SX HD6433837H HD6433837SH ...
Page 22
Internal Block Diagram Figure 1.1 shows a block diagram of the H8/3834 Series. P1 /TMOW 0 P1 /TMOFL 1 P1 /TMOFH 2 P1 /TMIG 3 P1 /PWM 4 P1 /IRQ /TMIB /IRQ /TMIC 6 2 /IRQ ...
Page 23
Pin Arrangement and Functions 1.3.1 Pin Arrangement The pin arrangement of the H8/3834 Series is shown in figures 1.2 and 1.3. 100 ...
Page 24
...
Page 25
Pin Functions Table 1.2 outlines the pin functions of the H8/3834 Series. Table 1.2 Pin Functions FP-100B Type Symbol TFP-100B FP-100A Power V 31 source pins ...
Page 26
Table 1.2 Pin Functions (cont) FP-100B Type Symbol TFP-100B FP-100A RES System 9 control MDO 10 TEST 3 IRQ Interrupt 88 0 IRQ pins 82 1 IRQ 83 2 IRQ 84 3 IRQ 11 4 WKP ...
Page 27
Table 1.2 Pin Functions (cont) FP-100B Type Symbol TFP-100B FP-100A Timer pins TMOFH 79 TMIG 80 14-bit PWM PWM 81 pin I/O ports 100 ...
Page 28
Table 1.2 Pin Functions (cont) FP-100B Type Symbol TFP-100B FP-100A I/O ports ...
Page 29
Table 1.2 Pin Functions (cont) FP-100B Type Symbol TFP-100B FP-100A Serial com- TXD 87 munication interface SCK 85 3 (SCI) A 100 converter ADTRG 11 LCD COM to 32 ...
Page 30
Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise, optimized instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. General-register ...
Page 31
Address Space The H8/300L CPU supports an address space kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 shows the register structure ...
Page 32
Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H ...
Page 33
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For ...
Page 34
Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR ...
Page 35
Data Formats in General Registers The general register data formats are shown in figure 2.3. Data Type Register No. 7 1-bit data RnH 7 1-bit data RnL 7 Byte data RnH MSB Byte data RnL 15 Word data Rn ...
Page 36
Memory Data Formats Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address ...
Page 37
Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No. Address Modes 1 Register direct 2 Register indirect ...
Page 38
Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address ...
Page 39
Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 ...
Page 40
Table 2.2 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register direct Register indirect, @ Register indirect with displacement, ...
Page 41
Table 2.2 Effective Address Calculation (cont) Addressing Mode and No. Instruction Format 5 Absolute address @aa abs @aa: abs 6 Immediate #xx IMM #xx: IMM 7 Program-counter relative ...
Page 42
Table 2.2 Effective Address Calculation (cont) Addressing Mode and No. Instruction Format 8 Memory indirect, @@aa abs Notation: rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address Effective Address ...
Page 43
Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Instructions Data transfer MOV, PUSH* Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, ...
Page 44
Notation Rd General register (destination) Rs General register (source) Rn General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag ...
Page 45
Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size* MOV B/W POP W PUSH W Note: * Size: Operand size B: Byte W: Word ...
Page 46
Notation: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer ...
Page 47
Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Instruction Size* Function ADD B/W Rd ± Rs SUB Performs addition or subtraction on data in two general registers, or addition on immediate data and data in ...
Page 48
Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Operation Instructions Instruction Size* Function AND B Rd Performs a logical AND operation on a general register and another general register or immediate data ...
Page 49
Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions Notation: op: Operation field rm, rn: Register field IMM: Immediate data ...
Page 50
Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 Sets a specified bit general register or memory operand. The ...
Page 51
Table 2.8 Bit-Manipulation Instructions (cont) Instruction Size* Function BXOR B C XORs the C flag with a specified bit in a general register or memory operand, and stores the result in the C flag. BIXOR B C XORs the C ...
Page 52
Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 ...
Page 53
Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont IMM ...
Page 54
Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Function Bcc — Branches to the designated address if the specified condition is true. The branching conditions are ...
Page 55
Notation: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes disp ...
Page 56
System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction Size* Function RTE — Returns from an exception-handling routine SLEEP — Causes a transition from active ...
Page 57
Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction Instruction Size Function EEPMOV — If R4L repeat until else next; Block transfer instruction. ...
Page 58
Basic Operational Timing CPU operation is synchronized by a system clock ( ) or a subclock ( clock signals see section 4, Clock Pulse Generators. The period from a rising edge of or the next rising edge is called ...
Page 59
Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions ...
Page 60
Three-State Access to On-Chip Peripheral Modules T or SUB Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) 2.7 CPU States ...
Page 61
CPU state Reset state The CPU is initialized. execution state Program halt state A state in which some or all of the chip functions are stopped to conserve power Exception- handling state A transient state entered when the CPU changes ...
Page 62
Reset state Reset occurs Program halt state 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one ...
Page 63
Memory Map 2.8.1 Memory Map Figure 2.16 shows the H8/3832 memory map. Figure 2.17 shows the H8/3833 memory map. Figure 2.18 shows the H8/3834 memory map. Figure 2.19 shows the H8/3835 memory map. Figure 2.20 shows the H8/3836 memory ...
Page 64
H'0000 H'0029 H'002A H'5FFF H'F740 H'F77F H'FB80 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFFF Note: The LCD RAM addresses are the addresses after a reset. * Interrupt vector area On-chip ROM Reserved * LCD RAM (64 bytes) Reserved On-chip RAM 32-byte serial ...
Page 65
H'0000 H'0029 H'002A H'7FFF H'F740 H'F77F H'FB80 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFFF Note: The LCD RAM addresses are the addresses after a reset Interrupt vector area On-chip ROM Reserved * LCD RAM (64 bytes) Reserved On-chip RAM 32-byte ...
Page 66
H'0000 H'0029 H'002A H'9FFF H'F740 H'F77F H'F780 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFFF Note: The LCD RAM addresses are the addresses after a reset. * Interrupt vector area On-chip ROM Reserved LCD RAM (64 bytes) * On-chip RAM 32-byte serial data ...
Page 67
H'0000 H'0029 H'002A H'BFFF H'F740 H'F77F H'F780 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFFF Note: * The LCD RAM addresses are the addresses after a reset. 50 Interrupt vector area On-chip ROM Reserved LCD RAM (64 bytes) * On-chip RAM 32-byte serial ...
Page 68
H'0000 H'0029 H'002A H'EDFF H'F740 H'F77F H'F780 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFFF Note: The LCD RAM addresses are the addresses after a reset. * Interrupt vector area On-chip ROM Reserved LCD RAM (64 bytes) * On-chip RAM 32-byte serial data ...
Page 69
LCD RAM Address Relocation After a reset, the LCD RAM area is located at addresses H'F740 to H'F77F. However, this area can be relocated by setting the LCD RAM relocation register (RLCTR) bits. The LCD RAM relocation register is ...
Page 70
Application Notes 2.9.1 Notes on Data Access Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are ...
Page 71
H'0000 Interrupt vector area (42 bytes) H'0029 H'002A On-chip ROM *2 H'7FFF Reserved H'F740 LCD RAM H'F77F Reserved *3 H'FB80 On-chip RAM H'FF7F H'FF80 32-byte serial data buffer H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Notes: The above example ...
Page 72
Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers ...
Page 73
Example 2: When a BSET instruction is executed on port 3 Here a BSET instruction is executed designating port 3. P3 and P3 are designated as input pins, with a low-level signal input signal at P3 ...
Page 74
As a result of this operation, bit 0 in PDR3 becomes 1, and P3 However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data in a work ...
Page 75
Bit Manipulation in a Register Containing a Write-Only Bit Example 3: When a BCLR instruction is executed on PCR3 of port 3 In this example, the port 3 control register PCR3 is accessed by a BCLR instruction the ...
Page 76
As a result of this operation, bit 0 in PCR3 becomes 0, making P3 and 6 in PCR3 change that P3 To avoid this problem, store a copy of the PCR3 data in a work area in ...
Page 77
Table 2.12 Registers with shared addresses Register Name Timer counter B and timer load register B Timer counter C and timer load register C Port data register 1* Port data register 2* Port data register 3* Port data register 4* ...
Page 78
Notes on Use of the EEPMOV Instruction The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified the address specified by R6 ...
Page 79
62 ...
Page 80
Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3834 Series when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Exception Handling Types and Priorities Priority ...
Page 81
Reset exception handling takes place as follows. The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. The PC is loaded from the reset ...
Page 82
RES MD0 Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 3.2 Reset Sequence (when MD0 Pin is Low) ...
Page 83
Interrupts 3.3.1 Overview The interrupt sources include 13 external interrupts (WKP internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with ...
Page 84
Table 3.2 Interrupt Sources and Priorities (cont) Priority Interrupt Source High Timer FL Timer FH Timer G SCI2 SCI3 A/D converter (SLEEP instruction Low executed) Note: Vector addresses H'0002 to H'0007 are reserved and cannot be used. 3.3.2 Interrupt Control ...
Page 85
IRQ Edge Select Register (IEGR) Bit 7 — Initial value 1 Read/Write — IEGR is an 8-bit read/write register, used to designate whether pins IRQ edge sensing or falling edge sensing. Bits 7 to 5—Reserved Bits: Bits ...
Page 86
Edge Select (IEG0): Bit 0 selects the input sensing of pin IRQ Bit 0—IRQ 0 Bit 0: IEG0 Description Falling edge of IRQ 0 Rising edge of IRQ 1 Interrupt Enable Register 1 (IENR1) Bit 7 IENTA IENS1 Initial value ...
Page 87
Bits 4 to 0—IRQ to IRQ Interrupt Enable (IEN4 to IEN0): Bits enable or disable IRQ IRQ interrupt requests. 0 Bit n: IENn Description Disables interrupt request IRQn 0 Enables interrupt request IRQn 1 ...
Page 88
Bit 4—Timer G Interrupt Enable (IENTG): Bit 4 enables or disables timer G input capture and overflow interrupt requests. Bit 4: IENTG Description 0 Disables timer G interrupts 1 Enables timer G interrupts Bit 3—Timer FH Interrupt Enable (IENTFH): Bit ...
Page 89
Interrupt request register 1 (IRR1) Bit 7 IRRTA IRRS1 Initial value 0 Read/Write R/W* Note: * Only a write of 0 for flag clearing is possible. IRR1 is an 8-bit read/write register, in which the corresponding bit is set to ...
Page 90
Interrupt Request Register 2 (IRR2) Bit 7 IRRDT IRRAD Initial value 0 Read/Write R/W* Note: * Only a write of 0 for flag clearing is possible. IRR2 is an 8-bit read/write register, in which the corresponding bit is set to ...
Page 91
Bit 4—Timer G Interrupt Request Flag (IRRTG) Bit 4: IRRTG Description 0 Clearing conditions: When IRRTG = cleared by writing 0 1 Setting conditions: When pin TMIG is set to TMIG input and the designated signal edge ...
Page 92
Bit 0—Timer B Interrupt Request Flag (IRRTB) Bit 0: IRRTB Description 0 Clearing conditions: When IRRTB = cleared by writing 0 1 Setting conditions: When the timer B counter value overflows (goes from H'FF to H'00) Wakeup ...
Page 93
When an interrupt exception handling request is received for interrupts WKP bit is set to 1. The vector number for interrupts WKP assigned the same vector number, the interrupt source must be determined by the exception handling routine. Interrupts IRQ ...
Page 94
If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.5. The PC value pushed onto ...
Page 95
Program execution state IRRIO = 1 Yes IENO = 1 Yes Yes PC contents saved CCR contents saved I 1 Branch to interrupt handling routine Notation: PC: Program counter CCR: Condition code register I: I bit of ...
Page 96
SP – – – – (R7) Stack area Prior to start of interrupt exception handling Notation Upper 8 bits of program counter (PC Lower 8 bits of ...
Page 97
Figure 3.6 Interrupt Sequence ...
Page 98
Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item Waiting time for completion of ...
Page 99
SP BSR instruction SP set to H'FEFF Notation Upper byte of program counter Lower byte of program counter L R1L: General register R1L SP: Stack pointer Figure 3.7 Operation when Odd Address is Set in ...
Page 100
Table 3.5 Conditions under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 Conditions IRR1 IRRI4 When PMR2 bit IRQ4 is changed from while pin IRQ IEGR bit IEG4 = 0. When ...
Page 101
Figure 3.8 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the ...
Page 102
Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator ...
Page 103
System Clock Generator Clock pulse can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator providing external clock input. Connecting a Crystal Oscillator: Figure 4.2 shows a typical method of connecting ...
Page 104
Connecting a Ceramic Oscillator: Figure 4.4 shows a typical method of connecting a ceramic oscillator. OSC 1 OSC 2 Figure 4.4 Typical Connection to Ceramic Oscillator Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic ...
Page 105
External Clock Input Method: Connect an external clock signal to pin OSC OSC open. Figure 4.6 shows a typical connection. 2 OSC 1 OSC 2 Figure 4.6 External Clock Input (Example) Frequency Oscillator Clock ( Duty cycle 45% to 55% ...
Page 106
Figure 4.8 shows the equivalent circuit of the 32.768-kHz crystal oscillator Figure 4.8 Equivalent Circuit of 32.768-kHz Crystal Oscillator 2. Inputting an external clock (H8/3832S, H8/3833S, H8/3834S, H8/3835S, H8/3836S, H8/3837S only) (1) Circuit configuration An external ...
Page 107
External clock Input a square waveform to the X LCD, with a subclock (øw) clock selected, do not stop the clock supply to the X Figure 4.10 External Subclock Timing The DC characteristics and timing of an external clock ...
Page 108
Pin Connection when Not Using Subclock: When the subclock is not used, connect pin X V and leave pin X open, as shown in figure 4. Figure 4.9 Pin Connection when Not Using Subclock 4.4 Prescalers The H8/3834 ...
Page 109
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA). Output from prescaler W can be used to drive timer A, in which case timer A functions as a time base ...
Page 110
Section 5 Power-Down Modes 5.1 Overview The H8/3834 Series has seven modes of operation after a reset. These include six power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the seven operation modes. Table ...
Page 111
Reset state Program halt state SSBY = 1, TMA3 = 0, LSON = 0 Standby mode SSBY = 1, TMA3 = 1 Watch mode : Transition caused by exception handling A transition between different modes cannot be made to occur ...
Page 112
Table 5.2 Internal State in Each Operation Mode Active Mode High Function Speed System clock oscillator Functions Subclock oscillator Functions CPU Instructions Functions operation RAM Registers I/O External IRQ Functions 0 interrupts IRQ 1 IRQ 2 IRQ 3 IRQ 4 ...
Page 113
System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.3 System Control Register Name System control register 1 System control register 2 System Control Register 1 (SYSCR1) Bit 7 SSBY ...
Page 114
Bit 6: STS2 Bit 5: STS1 Note: * Don’t care Bit 3—Low Speed on Flag (LSON): This bit chooses the system clock ( ) or subclock ( the CPU operating clock when watch mode is ...
Page 115
Bit 3—Direct Transfer on Flag (DTON): This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the ...
Page 116
Sleep Mode 5.2.1 Transition to Sleep Mode The system goes from active mode to sleep mode when a SLEEP instruction is executed while the SSBY and LSON bits in system control register 1 (SYSCR1) are cleared ...
Page 117
Clearing Standby Mode Standby mode is cleared by an interrupt (IRQ Clearing by Interrupt: When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2–STS0 in SYSCR1 has elapsed, a stable system ...
Page 118
Transition to Standby Mode and Port Pin States The system goes from active (high-speed or medium-speed) mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit ...
Page 119
Clearing Watch Mode Watch mode is cleared by an interrupt (timer A, IRQ pin. Clearing by Interrupt: Watch mode is cleared when an interrupt is requested. The mode to which a transition is made depends on the settings of ...
Page 120
Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (timer A, timer C, timer G, IRQ ) low input at the RES pin. WKP 7 Clearing by Interrupt: When an interrupt is requested, subsleep mode ...
Page 121
Active (medium-speed) Mode 5.7.1 Transition to Active (medium-speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared transition to active (medium-speed) mode results from IRQ mode, ...
Page 122
If the direct transfer interrupt is disabled in interrupt enable register 2 (IENR2), a transition is made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is set ...
Page 123
Calculation of Direct Transfer Time before Transition Time Required before Direct Transfer from Active (High-speed) Mode to Active (Medium- Speed) Mode: A direct transfer is made from active (high-speed) mode to active (medium-speed) mode when a SLEEP instruction is ...
Page 124
Direct transfer time = (number of states for SLEEP instruction execution + number of Example: Direct transfer time for the H8/3834 Series (when CPU clock frequency is ...
Page 125
108 ...
Page 126
Overview The H8/3832 has 16 kbytes of on-chip ROM, while the H8/3833 has 24 kbytes, the H8/3834 has 32 kbytes, the H8/3835 has 40 kbytes, the H8/3836 has 48 kbytes, and the H8/3837 has 60 kbytes. The ROM is ...
Page 127
H8/3834 PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard ...
Page 128
H8/3834 FP-100A FP-100B ...
Page 129
Address in MCU mode H'0000 H'7FFF Figure 6.3 H8/3834 Memory Map in PROM Mode Note: When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'7FFF. 112 Address in PROM mode H'0000 On-chip PROM H'7FFF ...
Page 130
H8/3834 Programming The write, verify, and other modes are selected as shown in table 6.3 in H8/3834 PROM mode. Table 6.3 Mode Selection in H8/3834 PROM Mode CE Mode Write L Verify H Programming disabled H Notation: L: Low ...
Page 131
Yes No n < 25 Error Figure 6.4 High-Performance Programming Flowchart 114 Start Set write/verify mode V = 6 Address = Write time ...
Page 132
Table 6.4 DC Characteristics (Conditions 6.0 V ±0. Item Input high OE, CE level voltage Input low OE, CE level voltage ...
Page 133
Table 6.5 AC Characteristics (Conditions 6.0 V ±0. Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time V setup time PP Programming pulse width ...
Page 134
Address t AS Data Input data VPS VCS OPW Note defined by the value given in ...
Page 135
H8/3837 PROM Mode 6.4.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard ...
Page 136
H8/3837 FP-100A FP-100B ...
Page 137
Address in MCU mode H'0000 H'EDFF Note read in PROM mode, this address area returns unpredictable output data. When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If address H'EE00 and higher ...
Page 138
H8/3837 Programming The write, verify, and other modes are selected as shown in table 6.8 in H8/3837 PROM mode. Table 6.8 Mode Selection in H8/3837 PROM Mode CE OE Mode Write L H Verify L L Programming L L ...
Page 139
Yes Error Figure 6.8 High-Speed, High-Reliability Programming Flow Chart 122 Start Set write/verify mode V = 6 Address = Write ...
Page 140
Table 6.9 and table 6.10 give the electrical characteristics in programming mode. Table 6.9 DC Characteristics (preliminary) (Conditions 6.0 V ±0. Item Input high OE, CE, PGM level ...
Page 141
Table 6.10 AC Characteristics (Conditions 6.0 V ±0. Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time V setup time PP Programming pulse width ...
Page 142
Figure 6.9 shows a write/verify timing diagram. Address t AS Data Input data VPS VCS CES PGM OE t Note: * ...
Page 143
Programming Precautions Use the specified programming voltage and timing. The programming voltage in PROM mode (V permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C101 ...
Page 144
Reliability of Programmed Data A highly effective way of assuring data retention characteristics after programming is to screen the chips by baking them at a temperature of 150°C. High-temperature baking is a screening method that quickly eliminates PROM memory ...
Page 145
128 ...
Page 146
Overview The H8/3832, H8/3833 and H8/3834 have 1 kbyte of high-speed static RAM on-chip, while the H8/3835, H8/3836, and H8/3837 each have 2 kbytes. The RAM is connected to the CPU by a 16- bit data bus, allowing high-speed ...
Page 147
130 ...
Page 148
Overview The H8/3834 Series is provided with eight 8-bit I/O ports, one 4-bit I/O port, one 3-bit I/O port, one 8-bit input-only port, one 4-bit input-only port, and one 1-bit input-only port. Table 8.1 indicates the functions of each ...
Page 149
Table 8.1 Port Functions (cont) Port Description Port 3 8-bit I/O port Input pull-up MOS option High-current port Port 4 1-bit input-only port P4 3-bit I/O port Port 5 8-bit I/O port Input pull-up MOS option Port 6 8-bit I/O ...
Page 150
Port 1 8.2.1 Overview Port 8-bit I/O port. Figure 8.1 shows its pin configuration. 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration. Table 8.2 Port 1 Registers Name Port data register ...
Page 151
Port Data Register 1 (PDR1) Bit Initial value 0 Read/Write R/W PDR1 is an 8-bit register that stores data for pins P1 are set to 1, the values stored in PDR1 are read, regardless of the actual ...
Page 152
Port Mode Register 1 (PMR1) Bit 7 IRQ3 Initial value 0 Read/Write R/W PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'00. Bit 7—P1 /IRQ /TMIF ...
Page 153
Bit 4—P1 /PWM Pin Function Switch (PWM): This bit selects whether pin PWM. 4 Bit 4: PWM Description 0 Functions Functions as PWM output pin Bit 3—P1 /TMIG Pin Function Switch (TMIG): ...
Page 154
Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Pin Functions and Selection Method P1 /IRQ /TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in ...
Page 155
Table 8.3 Port 1 Pin Functions (cont) Pin Pin Functions and Selection Method P1 /PWM The pin function depends on bit PWM in PMR1 and bit PCR1 4 PWM PCR1 4 Pin function P1 /TMIG The pin function depends on ...
Page 156
Pin States Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4 Port 1 Pin States Pins Reset P1 /IRQ /TMIF High impedance P1 /IRQ /TMIC /IRQ /TMIB 5 1 ...
Page 157
Port 2 8.3.1 Overview Port 8-bit I/O port. Figure 8.2 shows its pin configuration. 8.3.2 Register Configuration and Description Table 8.5 shows the port 2 register configuration. Table 8.5 Port 2 Registers Name Port data register ...
Page 158
Port Data Register 2 (PDR2) Bit Initial value 0 Read/Write R/W PDR2 is an 8-bit register that stores data for pins P2 are set to 1, the values stored in PDR2 are read, regardless of the actual ...
Page 159
Bits 7 to 6—Reserved Bits: Bits are reserved; they are always read as 1, and cannot be modified. Bit 5—P3 /SO Pin PMOS Control (POF2): This bit controls the on/off state of the PMOS 5 2 transistor ...
Page 160
Bit 0: P2 /IRQ /ADTRG Pin Function Switch (IRQ4): This bit selects whether pin /IRQ /ADTRG is used Bit 0: IRQ4 Description 0 Functions as P2 Functions as IRQ 1 Note: See 12.3.2, ...
Page 161
Pin Functions Table 8.6 shows the port 2 pin functions. Table 8.6 Port 2 Pin Functions Pin Pin Functions and Selection Method Input or output is selected as follows by the bit settings in PCR2. 7 ...
Page 162
Port 3 8.4.1 Overview Port 8-bit I/O port, configured as shown in figure 8.3. 8.4.2 Register Configuration and Description Table 8.8 shows the port 3 register configuration. Table 8.8 Port 3 Registers Name Port data register ...
Page 163
Port Data Register 3 (PDR3) Bit Initial value 0 Read/Write R/W PDR3 is an 8-bit register that stores data for port 3 pins P3 bits are set to 1, the values stored in PDR3 are read, regardless ...
Page 164
Port Mode Register 3 (PMR3) Bit 7 CS Initial value 0 Read/Write R/W PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'00. Bit 7—P3 /CS Pin ...
Page 165
Bit 3—P3 /SCK Pin Function Switch (SCK2): This bit selects whether pin SCK . 3 2 Bit 3: SCK2 Description 0 Functions Functions as SCK Bit 2—P3 /SO Pin Function Switch ...
Page 166
Pin Functions Table 8.9 shows the port 3 pin functions. Table 8.9 Port 3 Pin Functions Pin Pin Functions and Selection Method P3 /CS The pin function depends on bit CS in PMR3 and bit PCR3 7 CS PCR3 ...
Page 167
Table 8.9 Port 3 Pin Functions (cont) Pin Pin Functions and Selection Method P3 /SO The pin function depends on bit SO1 in PMR3 and bit PCR3 2 1 SO1 PCR3 2 Pin function P3 /SI The pin function depends ...
Page 168
Pin States Table 8.10 shows the port 3 pin states in each operating mode. Table 8.10 Port 3 Pin States Pins Reset Sleep P3 /CS High- Retains 7 impedance previous P3 /STRB 6 state P3 / ...
Page 169
Port 4 8.5.1 Overview Port 4 consists of a 3-bit I/O port and a 1-bit input port, and is configured as shown in figure 8.4. 8.5.2 Register Configuration and Description Table 8.11 shows the port 4 register configuration. Table ...
Page 170
Port Data Register 4 (PDR4) Bit 7 — Initial value 1 Read/Write — PDR4 is an 8-bit register that stores data for port 4 pins P4 bits are set to 1, the values stored in PDR4 are read, regardless of ...
Page 171
Pin Functions Table 8.12 shows the port 4 pin functions. Table 8.12 Port 4 Pin Functions Pin Pin Functions and Selection Method P4 /IRQ The pin function depends on the IRQ0 bit setting in PMR2 IRQ0 Pin ...
Page 172
Pin States Table 8.13 shows the port 4 pin states in each operating mode. Table 8.13 Port 4 Pin States Pins Reset Sleep P4 /IRQ High- Retains 3 0 impedance previous P4 /TXD 2 state P4 /RXD 1 P4 ...
Page 173
Register Configuration and Description Table 8.14 shows the port 5 register configuration. Table 8.14 Port 5 Registers Name Port data register 5 Port control register 5 Port pull-up control register 5 Port mode register 5 Port Data Register 5 ...
Page 174
Port Pull-up Control Register 5 (PUCR5) Bit 7 PUCR5 PUCR5 7 Initial value 0 Read/Write R/W PUCR5 bits control the on/off state of pin P5 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the ...
Page 175
Pin Functions Table 8.15 shows the port 5 pin functions. Table 8.15 Port 5 Pin Functions Pin Pin Functions and Selection Method P5 /WKP / The pin function depends on bit WKPn in PMR5, bit PCR5 7 7 SEG ...
Page 176
MOS Input Pull-Up Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for ...
Page 177
Register Configuration and Description Table 8.17 shows the port 6 register configuration. Table 8.17 Port 6 Registers Name Port data register 6 Port control register 6 Port pull-up control register 6 Port Data Register 6 (PDR6) Bit 7 P6 ...
Page 178
Port Pull-Up Control Register 6 (PUCR6) Bit 7 PUCR6 PUCR6 7 Initial value 0 Read/Write R/W PUCR6 controls whether the MOS pull-up of each port 6 pin P6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 ...
Page 179
Pin States Table 8.19 shows the port 6 pin states in each operating mode. Table 8.19 Port 6 Pin States Pins Reset P6 /SEG to High /SEG impedance 0 9 Note high-level signal is ...
Page 180
Port 7 8.8.1 Overview Port 8-bit I/O port, configured as shown in figure 8.7. 8.8.2 Register Configuration and Description Table 8.20 shows the port 7 register configuration. Table 8.20 Port 7 Registers Name Port data register ...
Page 181
Upon reset, PDR7 is initialized to H'00. Port Control Register 7 (PCR7) Bit 7 PCR7 PCR7 7 Initial value 0 Read/Write W PCR7 is an 8-bit register for controlling whether each of the port 7 pins P7 input pin or ...
Page 182
Pin States Table 8.22 shows the port 7 pin states in each operating mode. Table 8.22 Port 7 Pin States Pins Reset P7 /SEG to High /SEG impedance 0 17 8.9 Port 8 8.9.1 Overview Port ...
Page 183
Port Data Register 8 (PDR8) Bit Initial value 0 Read/Write R/W PDR8 is an 8-bit register that stores data for port 8 pins P8 bits are set to 1, the values stored in PDR8 are read, regardless ...
Page 184
Pin Functions Table 8.24 shows the port 8 pin functions. Table 8.24 Port 8 Pin Functions Pin Pin Functions and Selection Method P8 /SEG to The pin function depends on bit PCR8 /SEG LPCR ...
Page 185
Port 9 8.10.1 Overview Port 8-bit I/O port configured as shown in figure 8.9. 8.10.2 Register Configuration and Description Table 8.26 shows the port 9 register configuration. Table 8.26 Port 9 Registers Name Port data register ...
Page 186
Upon reset, PDR9 is initialized to H'00. Port Control Register 9 (PCR9) Bit 7 PCR9 PCR9 7 Initial value 0 Read/Write W PCR9 is an 8-bit register for controlling whether each of the port 9 pins P9 input or output ...
Page 187
Table 8.27 Port 9 Pin Functions (cont) Pin Pin Functions and Selection Method P9 /SEG /DO The pin function depends on bit PCR9 5 38 SGS0 in LPCR. SGS3 to SGS0 SGX PCR9 5 Pin function P9 /SEG /M The ...
Page 188
Pin States Table 8.28 shows the port 9 pin states in each operating mode. Table 8.28 Port 9 Pin States Pins Reset P9 /SEG /CL High impedance P9 /SEG / /SEG /DO ...
Page 189
Register Configuration and Description Table 8.29 shows the port A register configuration. Table 8.29 Port A Registers Name Port data register A Port control register A Port Data Register A (PDRA) Bit 7 — Initial value 1 Read/Write — ...
Page 190
Pin Functions Table 8.30 gives the port A pin functions. Table 8.30 Port A Pin Functions Pin Pin Functions and Selection Method PA /COM The pin function depends on bit PCRA 3 4 SGX, and SGS3 to SGS0 in ...
Page 191
Table 8.30 Port A Pin Functions (cont) Pin Pin Functions and Selection Method PA /COM The pin function depends on bit PCRA0 in PCRA, and bits SGX and SGS3 SGS0 in LPCR. SGS3 to SGS0 SGX PCRA ...
Page 192
Port B 8.12.1 Overview Port 8-bit input-only port, configured as shown in figure 8.11. 8.12.2 Register Configuration and Description Table 8.32 shows the port B register configuration. Table 8.32 Port B Register Name Port data register ...
Page 193
Port C 8.13.1 Overview Port 4-bit input-only port, configured as shown in figure 8.12. 8.13.2 Register Configuration and Description Table 8.33 shows the port C register configuration. Table 8.33 Port C Register Name Port data register ...
Page 194
Overview The H8/3834 Series provides five timers (timers and G) on-chip. Table 9.1 outlines the functions of timers and G. Table 9.1 Timer Functions Name Functions Timer A 8-bit timer Interval ...
Page 195
Timer A 9.2.1 Overview Timer 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz or ...
Page 196
Block Diagram Figure 9.1 shows a block diagram of timer A. 1 / TMOW / Notation: TMA: Timer mode register A TCA: Timer ...
Page 197
Register Configuration Table 9.3 shows the register configuration of timer A. Table 9.3 Timer A Registers Name Timer mode register A Timer counter A 9.2.2 Register Descriptions Timer Mode Register A (TMA) Bit 7 TMA7 Initial value 0 Read/Write R/W ...
Page 198
Bits 3 to 0—Internal Clock Select (TMA3 to TMA0): Bits select the clock input to TCA. Bit 3: Bit 2: Bit 1: TMA3 TMA2 TMA1 ...
Page 199
Timer Operation Interval Timer Operation: When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to ...
Page 200
Timer A Operation States Table 9.4 summarizes the timer A operation states. Table 9.4 Timer A Operation States Operation Mode Reset Active TCA Interval Reset Clock time base Reset TMA Reset Note: When real-time clock time base function is ...