HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 189

MCU 5V 32K PB-FREE 100-QFP

HD6473834HV

Manufacturer Part Number
HD6473834HV
Description
MCU 5V 32K PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD6473834HV

Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
71
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473834HV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6473834HV
Manufacturer:
RENESAS
Quantity:
2 120
8.11.2
Table 8.29 shows the port A register configuration.
Table 8.29 Port A Registers
Name
Port data register A
Port control register A
Port Data Register A (PDRA)
PDRA is an 8-bit register that stores data for port A pins PA
bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If port A is
read while PCRA bits are cleared to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
Port Control Register A (PCRA)
PCRA is an 8-bit register for controlling whether each of the port A pins PA
an input or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCRA and in PDRA are valid only
when the corresponding pin is designated in LPCR as a general I/O pin.
Upon reset, PCRA is initialized to H'F0.
PCRA is a write-only register. All bits are read as 1.
172
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Register Configuration and Description
7
1
7
1
6
1
6
1
Abbrev.
PDRA
PCRA
5
1
5
1
R/W
R/W
W
4
1
4
1
PCRA
3
R/W
PA
to PA
W
Initial Value
H'F0
H'F0
3
0
3
0
3
3
0
. If port A is read while PCRA
PCRA
R/W
PA
W
2
0
2
0
2
2
3
to PA
PCRA
R/W
PA
Address
H'FFDD
H'FFED
W
1
0
1
0
0
1
functions as
1
PCRA
R/W
PA
W
0
0
0
0
0
0

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