M30876FJAGP#U3 Renesas Electronics America, M30876FJAGP#U3 Datasheet - Page 111

• Manufacturer Part Number: M30876FJAGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30876FJAGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 87 of 587
Figure 9.7
Processor Mode Register 2
b7 b6 b5 b4
NOTES:
1. Set the PM2 register after the PRC1 bit in the PRCR register is set to 1 (write enable).
2. Once bits PM22 and PM21 are set to 1, they cannot be set to 0 by a program.
3. When the PM21 bit is set to 1;
4. When the PM22 bit is set to 1;
5. When the PM25 bit is set to 1 (CAN clock is fCAN), set the PM24 bit to 1 before accessing the CAN-associated registers.
• the CPU clock does not stop even if the WAIT instruction is executed
• writes to the following bits have no effect
• the on-chip oscillator starts oscillating and the on-chip oscillator clock becomes the count source of the watchdog timer
• write to the CM10 bit in the CM1 register is disabled (writing a 1 has no effect and the MCU does not enter stop mode)
• the watchdog timer keeps operating when the MCU is in wait mode or in hold state
- the CM02 bit in the CM0 register
- the CM05 bit in the CM0 register
- the CM07 bit in the CM0 register (CPU clock source is not changed)
- the CM10 bit in the CM1 register (the MCU does not enter stop mode)
- the CM17 bit in the CM1 register (CPU clock source is not changed)
- the CM20 bit in the CM2 register (oscillation stop detect function setting is not changed)
- all bits in registers PLC0 and PLC1 (PLL frequency synthesizer setting is not changed)
b3
0
b2
PM2 Register
b1
b0
0
Bit Symbol
PM21
PM22
PM24
PM25
PM26
PM27
(b0)
(b3)
Symbol
PM2
−
−
Reserved bit
System clock protect bit
WDT count source protect bit
Reserved bit
CPU clock select bit 3
CAN clock select bit
f2n clock source select bits
(1)
Bit Name
(2, 3)
Address
0013h
(2, 4)
Set to 0
0: Protects a clock by the PRCR register
1: Disables a clock change
0: CPU clock as count source for the watchdog
1: On-chip oscillator clock as count source for
Set to 0
0: Clock selected by the CM07 bit
1: Main clock
0: f1
1: fCAN
b7 b6
0 0: Clock selected by the CM21 bit
0 1: XIN clock (fXIND)
1 0: On-chip oscillator clock (fROC)
1 1: Do not set to this value
timer
the watchdog timer
(5)
Function
9. Clock Generation Circuits
After Reset
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW