M30876FJAGP#U3 Renesas Electronics America, M30876FJAGP#U3 Datasheet - Page 391

• Manufacturer Part Number: M30876FJAGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30876FJAGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 367 of 587
Figure 22.35
22.3.7
(1) When GiPOj register value is reloaded to the internal register at the base timer reset (RLD bit in the GiPOCRj register = 1)
(2) When GiPOj register value is reloaded to the internal register when written (RLD bit in the GiPOCRj register = 0)
Base timer i
Count source of
base timer
Base timer value
Read value from
the GiBT register
GiPOj register
OUTCi_ j pin
POijR bit in the IIO0IR to
IIO11IR register
Base timer i
Count source of
base timer
Base timer value
Read value from
the GiBT register
GiPOj register
OUTCi_ j pin
POijR bit in the IIO0IR to
IIO11IR register
i = 1, 2; j = 0 to 7; m: Setting value of the GiPOj register (0000h to FFFFh); n: Setting value of the GiPO0 register (0000h to FFFFh)
The above applies under the following conditions:
- Group 1: G1BCR1 register; bits RST2 and RST1 are set to 00b (base timer is not reset by matching the G1PO0 register)
- Group 2: Bits RST2 and RST0 in the G2BCR1 register are set to 000b (base timer is not reset by matching the G2PO0 register)
- GiPOCRj register: bits MOD2 to MOD0 are set to 010b (phase-delayed waveform output mode),
- m < n
The RLD bit in the GiPOCRj register determines whether the GiPOj register value is reloaded to the internal
register when the value is written, or when the base timer is reset. Figure 22.35 shows an operation example.
GiPOj Register Value Reload Timing Select Function (i = 1, 2; j = 0 to 7)
GiPOj Register Value Reload Timing Select Function Operation
FFFFh
FFFFh
0000h
0000h
the IVL bit is set to 0 (“L” output), and the INV bit is set to 0 (output not inverted)
m
"H"
m
"H"
n
"L"
n
"L"
1
0
1
0
bits UD1 and UD0 are set to 00b (counter increment mode)
Match
Match
m
m
m
m
m
m
m+1
m+1
m+1
m+1
n - m
fBTi
Match
n
n
n
n
n+1
n
Set to 0 by a program
n+1
22. Intelligent I/O (Waveform Generation Function)
FFFF 0000
FFFF 0000
FFFF 0000
FFFF 0000
65536 + n - m
65536 - n + m
fBTi
Set to 0 by a program
fBTi
n
m
Match
m
m
m+1
m+1
Match
n
n
Match
n+1
n
n+1
n
n
n+1
n+1